Backside Power Rail Formation Using Sacrificial Epitaxial Fill
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Solution Overview
Problem
Traditional semiconductor transistor architectures require larger areas due to intermixed power rails and signal lines, and traditional backside power sources increase transistor size, complicating the delicate balance between power distribution and signal lines.
Innovation Solution
The method involves forming backside power supply structures using a sacrificial fill material, such as silicon or silicon germanium, through an anisotropic dry etching process and selective epitaxial growth, which allows for self-aligned epitaxial source/drain structures and reduced transistor area by eliminating the need for post-etch wet clean processes and preserving oxide spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional front side power grid is used with intermixed power rails and signal lines, then power distribution is achieved, but the transistor area increases and the network becomes complex
Solution Approach 1:
The patent moves the power rail from the front side to the back side of the substrate, utilizing the third dimension (depth/vertical positioning) to separate power distribution from signal routing. This dimensional relocation eliminates the need for intermixed power and signal lines on the same plane, reducing network complexity while maintaining power distribution functionality.
Solution Approach 2:
The patent segments the substrate into front side (for transistors and signal lines) and back side (for power rails), allowing independent optimization of each layer. This segmentation enables simplified signal routing on the front side while power distribution is handled separately on the back side, reducing overall system complexity.
2Quantity of substance
If traditional backside power sources with vias extending into transistors are used, then power supply is achieved, but the transistor area increases
Solution Approach 1:
The patent extracts the power via from the transistor structure itself and relocates it to the back side of the substrate. Instead of having vias extend into the transistor active area from the front side, the power connection is established separately on the back side, removing the intrusive element that increases transistor area.
Solution Approach 2:
The power connection is moved from the front side (where it would occupy transistor area) to the back side of the substrate, utilizing the vertical dimension to separate power access from the transistor active area, thereby reducing the area occupied by each transistor.
3Quantity of substance
If buried power rails connecting to transistors are used, then power supply is achieved, but the transistor area increases
Solution Approach 1:
The patent removes the buried power rail structure from within the transistor area and relocates the power connection to the back side of the substrate. This extraction eliminates the need for lateral power rails that would occupy valuable transistor area, achieving power supply without area penalty.
Solution Approach 2:
The power distribution is moved from a lateral (in-plane) configuration to a vertical (through-substrate) configuration, accessing power from the back side rather than embedding rails within the transistor plane, thereby reducing the area required for each transistor.
4Manufacturing precision
If anisotropic dry etch process with chlorine gas is used to remove oxide layer, then selective removal from bottom portion of opening is achieved, but process complexity increases
Solution Approach 1:
The patent employs a self-aligned etch process where the oxide spacer automatically defines the etch termination point. The spacer serves as its own mask, eliminating the need for separate alignment steps and reducing process complexity despite the selective nature of the etching. The process is self-regulating based on the spacer geometry.
Solution Approach 2:
The patent utilizes specific etch parameters (chlorine gas chemistry, anisotropic etching mode) that provide inherent selectivity for removing oxide from the bottom portion of the opening while preserving the oxide spacer on the sidewalls. These parameter choices achieve high manufacturing precision through material-specific etching rates rather than complex process sequencing.
5Manufacturing precision
If selective epitaxial growth is used to grow sacrificial fill material, then fill selectivity is improved, but process time increases
Solution Approach 1:
The patent achieves selective epitaxial growth by controlling growth parameters (temperature, pressure, gas composition) to favor growth on specific crystal planes. By optimizing these parameters, the process achieves high selectivity (4:1 ratio) while minimizing total growth time, as the selective growth occurs rapidly on the exposed silicon surfaces.
Solution Approach 2:
The patent performs preliminary surface preparation (oxide removal, surface activation) before epitaxial growth to ensure rapid and selective growth occurs immediately upon exposure to the epitaxial environment. This preliminary action eliminates the need for extended growth times to achieve sufficient selectivity, as the conditions are pre-established for fast selective growth.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies transistor formation, increases transistor density, and prevents pinch-off voids and selectivity loss, enabling high-density transistor structures with improved connectivity and reduced area usage.
Implementation Method 1
performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas that removes the oxide layer from a field of the substrate and only from a bottom portion of the opening
Implementation Method 2
epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr
Implementation Method 3
epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas
Data Source
AI summary
A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.