Back-Side Power Rails for Integrated Circuit Power Gating

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As semiconductor integrated circuits (ICs) become smaller and more complex, operating voltages are reduced, leading to increased power consumption due to resistance, and power gating techniques are used to reduce power consumption but can be inefficient.

Innovation Solution

The implementation of a header and footer circuit configuration with parallel power rails on the back-side and front-side of a wafer, respectively, to supply different voltages to gated and ungated circuits, using PMOS and NMOS transistors to manage power states based on control signals, thereby reducing resistance and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If operating voltages are reduced to enable smaller and more complex ICs, then IC size and complexity can be increased, but power consumption increases due to resistance

Engineering Contradiction:
ImproveIC complexityVSAvoidpower consumption
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The IC is divided into multiple voltage domains (first voltage domain and second voltage domain) with separate power supply rails. This segmentation allows different circuits to operate at different voltages, reducing overall power consumption while enabling increased IC complexity through specialized functional blocks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the IC are provided with different operating voltages tailored to their specific requirements. The first voltage domain receives a first voltage while the second voltage domain receives a second voltage, optimizing power efficiency for each local region while maintaining overall IC functionality.

Inventive Principle:
Principle #3Local quality

2Loss of energy

If power gating is used to reduce power consumption, then power efficiency can be improved, but the technique becomes inefficient

Engineering Contradiction:
Improvepower consumptionVSAvoidpower management efficiency
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The power supply system dynamically adjusts voltage delivery based on operational requirements. Power rails are selectively activated or deactivated for different voltage domains, and voltage levels are adjusted in response to circuit activity, providing dynamic power management that overcomes the inefficiencies of static power gating.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes voltage parameters adaptively by providing different voltage levels to different domains and adjusting power rail activation states. This dynamic parameter adjustment enables efficient power management that responds to actual circuit needs rather than relying on fixed power gating schemes.

Inventive Principle:
Principle #35Parameter changes

3Loss of energy

If multiple voltage domains are implemented, then power management efficiency can be improved, but device complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidvoltage domain configuration
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The power management circuit serves multiple functions by controlling power delivery to both the first and second voltage domains through a unified architecture. This multi-functional approach enables efficient power management across different voltage domains while avoiding the need for separate independent power management systems for each domain.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250275253A1Integrated circuit and method of forming the same
Publication Date: 2025.08.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250275253A1 patent drawing
  • US20250275253A1 patent drawing
  • US20250275253A1 patent drawing

AI summary

An integrated circuit includes a first and a second power rail on a back-side of a wafer and configured to supply a first voltage, a footer circuit coupled to the first and the second power rail, and configured to receive a second supply voltage, and to supply the first voltage to the first and the second power rail in response to a control signal, a third power rail on the back-side of the wafer, and configured to supply a third voltage, a fourth power rail on a front-side of the wafer and a fifth power rail on the back-side of the wafer. The fourth power rail and the fifth power rail are configured to supply the second voltage to the footer circuit. The fourth power rail includes a first set of conductors, each conductor of the first set of conductors is separated from one another in the first direction.