Backside Power Rail Structure With Self-Aligned Vias for Lower IR Drop
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Solution Overview
Problem
As integrated circuits scale down, power rails experience increased voltage drop and power consumption, necessitating improved power rail designs to enhance performance and reduce consumption.
Innovation Solution
Implementing backside power rails and self-aligned vias in semiconductor devices, which include wider metal tracks on the backside to connect to source/drain contacts, reducing the need for frontside contacts and lowering coupling capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If power rails are scaled down with integrated circuits, then device integration is improved, but voltage drop and power consumption increase
Solution Approach 1:
The patent introduces backside power rails that extend from the frontside through the substrate to the backside of the device. This three-dimensional power distribution approach adds a vertical dimension to the traditionally planar power rail structure, enabling wider effective power delivery paths without increasing footprint area, thereby reducing resistance and power consumption while maintaining high integration density.
Solution Approach 2:
The power distribution network is segmented into frontside power rails, backside power rails, and interconnect layers. This segmentation allows each component to be optimized independently - frontside rails for local power delivery, backside rails for high-current paths, and interconnect layers for signal routing - reducing overall power consumption through specialized optimization of each segment.
2Productivity
If power rails are scaled down with integrated circuits, then device integration is improved, but voltage drop increases
Solution Approach 1:
By extending power rails to the backside of the substrate, the invention creates additional vertical routing dimensions for power delivery. This allows power to reach distant components through multiple pathways (frontside rails, backside rails, and interconnect layers), reducing voltage drop by distributing the electrical load across a three-dimensional network rather than relying solely on scaled-down planar rails.
Solution Approach 2:
The backside power rails act as intermediary conductors between the frontside power distribution network and the active devices. These intermediate backside rails provide additional current pathways that mediate the power delivery process, reducing the burden on frontside rails and minimizing voltage drop across the entire power distribution network.
3Loss of energy
If wider metal tracks are used on backside, then power rail resistance is reduced, but device complexity increases
Solution Approach 1:
The invention utilizes the backside of the substrate as an additional dimensional space for power rail routing. By placing wider metal tracks on the backside rather than expanding the footprint on the frontside, the design reduces power rail resistance without increasing the device's planar dimensions, accepting increased fabrication complexity as a trade-off for improved electrical performance.
4Productivity
If backside power rails are implemented, then gate density is increased, but manufacturing complexity increases
Solution Approach 1:
The implementation of backside power rails utilizes the vertical dimension by routing power connections through the substrate to the backside. This three-dimensional approach enables higher gate density on the frontside by freeing up planar space, while the backside processing complexity is managed through specialized fabrication techniques for through-substrate via formation and backside metal deposition.
Data Source
AI summary
A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source/drain feature; and a power rail disposed under and electrically connected to the first via.