Backside Rail Layout for Variable Cell Height Routing
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Solution Overview
Problem
Existing chip layouts face challenges in efficiently managing power routing and signal routing due to congestion, particularly when integrating transistors with varying heights and complexities, which can lead to inefficiencies in circuit performance.
Innovation Solution
Implementing a chip design with backside rails that have uniform and variable pitches, combined with cells of uniform and variable heights, allowing for separate backside power distribution networks to alleviate routing congestion and enhance efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If cells with varying heights are integrated on the chip, then circuit functionality and performance are improved, but routing congestion increases
Solution Approach 1:
The chip is divided into multiple tiers or levels, with each tier containing cells of specific height ranges. This segmentation allows cells of different heights to be organized in distinct regions, reducing routing congestion by grouping similar-height cells together while still supporting overall height variation across the chip.
Solution Approach 2:
The patent introduces a vertical dimension (tier/level organization) to manage cell height variation. By organizing cells across multiple tiers rather than a single plane, the design accommodates varying cell heights while maintaining manageable routing complexity within each tier.
2Ease of manufacture
If backside rails with uniform pitch are used, then manufacturing simplicity is improved, but adaptability to variable cell heights deteriorates
Solution Approach 1:
The backside rail system is segmented into multiple sections, each serving a specific tier of cells. Within each section, rails maintain uniform pitch for manufacturing simplicity, while different sections can have different pitch values to accommodate the specific height requirements of different tiers.
Solution Approach 2:
Different regions of the chip receive tailored rail configurations. Areas with taller cells receive rails with larger pitch, while areas with shorter cells receive rails with smaller pitch, allowing each local region to be optimized for its specific cell height requirements while maintaining overall manufacturing feasibility.
3Quantity of substance
If power routing is integrated with signal routing, then device density is improved, but routing congestion and performance efficiency worsen
Solution Approach 1:
Power routing and signal routing are segmented into separate pathways or layers. Power rails are established independently from signal routes, allowing each to be optimized for its specific function without contributing to mutual congestion, while still achieving high device density through efficient space utilization.
Data Source
AI summary
A chip includes first backside rails, wherein each of the first backside rails extends in a first direction, and the first backside rails are spaced apart by a uniform pitch in a second direction perpendicular to the first direction. The chip also includes second backside rails, wherein each of the second backside rails extends in the first direction, and the second backside rails are spaced apart by a variable pitch in the second direction.