Backside Redistribution Layer Structure for 3D IC Thermal Routing
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Solution Overview
Problem
The scaling down of integrated circuits (ICs) has increased complexity, power dissipation, thermal management, and limited circuit areas, requiring advancements in IC processing and manufacturing to maintain efficiency and reduce costs while enhancing device performance.
Innovation Solution
A 3D integrated circuit structure is formed by bonding two semiconductor wafers with interconnect structures and conductive features, including through vias and backside metal routing features, to enhance thermal dissipation, electrical connectivity, and packaging efficiency, allowing for increased design flexibility and circuit packing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If IC geometry size is decreased to increase functional density, then production efficiency and cost are improved, but power dissipation and thermal management challenges worsen
Solution Approach 1:
The patent transitions from planar (2D) circuit layout to three-dimensional (3D) stacked architecture, enabling vertical interconnect through through-silicon vias (TSVs). This dimensional change allows heat to dissipate through additional vertical pathways and distributes power dissipation across multiple stacked layers, effectively managing thermal load while maintaining high functional density achieved through scaling.
Solution Approach 2:
The patent divides the integrated circuit into multiple separate semiconductor substrates that are stacked and interconnected. Each substrate can be independently optimized for specific functions (e.g., logic, memory, RF), allowing thermal management to be addressed at each layer level rather than as a monolithic system, thereby reducing overall power dissipation challenges.
2Area of moving object
If IC geometry size is decreased to increase functional density, then circuit area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the manufacturing process into modular steps: fabricating individual semiconductor substrates with their respective circuits, forming TSVs through each substrate, bonding substrates together in stack, and forming redistribution layers. This segmentation allows each module to be optimized and tested independently before final assembly, reducing overall manufacturing complexity despite the advanced 3D architecture.
Solution Approach 2:
The patent performs preliminary actions by pre-fabricating complete functional circuits on separate substrates before stacking, and pre-forming TSVs through each substrate before bonding. This allows each substrate to be optimized and validated independently, simplifying the final assembly process and reducing manufacturing complexity of the overall 3D structure.
3Ease of manufacture
If traditional planar IC structure is used, then manufacturing process is simpler, but thermal dissipation and electrical connectivity are limited
Solution Approach 1:
The patent introduces vertical dimension to the IC structure by stacking multiple semiconductor substrates and forming through-silicon vias for inter-layer connectivity. This 3D architecture provides additional thermal pathways through the stack and enables better heat distribution across multiple layers, significantly improving thermal dissipation compared to traditional planar structures while maintaining manufacturing feasibility through modular fabrication.
4Reliability
If functional density is increased through scaling, then device performance improves, but power dissipation worsens
Solution Approach 1:
The patent segments high-functional-density circuits across multiple separate substrates stacked in 3D configuration. Each substrate can be optimized for specific high-performance functions while the vertical stacking and TSV interconnect enable efficient power distribution and heat removal, thereby maintaining high device performance while managing power dissipation through distributed architecture.
Solution Approach 2:
By transitioning to 3D stacked architecture, the patent enables vertical power and signal distribution through TSVs, allowing heat to escape through additional vertical pathways and distributing power dissipation across multiple layers. This maintains high functional density and device performance while effectively managing the power dissipation that would otherwise concentrate in a planar configuration.
Data Source
AI summary
A method includes forming first IC devices on a first frontside of a first semiconductor substrate and second IC devices on a second frontside of a second semiconductor substrate; forming a first contact pad over the first IC devices from the first frontside and a second contact pad over the second IC device from the second frontside; bonding the first and second contact pads such that the first and second IC devices are electrically connected; and forming a conductive structure on a first backside of the first semiconductor substrate. The conductive structure includes a through via (TV), a backside metal (BSM) feature, and a backside redistribution layer (BRDL). The TV is extending through the first semiconductor substrate and electrically connected the first and second IC devices to the BRDL, and the BSM feature is extended into a portion of the first semiconductor substrate and electrically connected to the TV.