Backside Reveal Process for Integrated Circuit Devices
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Solution Overview
Problem
In three-dimensional integrated circuit (IC) devices, accessing the device layer from both the front and backside is challenging due to the inverse proportionality between via density and substrate thickness, making it difficult to effectively reveal the backside for further processing and interconnect formation.
Innovation Solution
A backside reveal process involving mechanical grinding, wet etching, and chemical mechanical planarization (CMP) using a selective slurry to remove the semiconductor substrate, exposing the backside while preserving the isolation oxide and allowing for higher density via formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the substrate thickness is reduced to increase via density, then via density is improved, but substrate mechanical strength deteriorates
Solution Approach 1:
The substrate removal process is segmented into multiple stages: mechanical grinding removes the bulk substrate thickness, wet etching removes additional substrate while allowing via formation, and CMP provides final planarization. This segmentation allows progressive substrate reduction without compromising structural integrity at any single step.
Solution Approach 2:
Via formation is performed preliminarily during the wet etching stage before complete substrate removal. This preliminary via formation allows subsequent substrate removal to proceed without compromising via structural support, resolving the contradiction between substrate thickness reduction and via density increase.
2Productivity
If mechanical grinding is used to remove substrate, then substrate removal efficiency is improved, but surface planarity deteriorates
Solution Approach 1:
The substrate removal process is divided into mechanical grinding for bulk removal (high productivity) followed by CMP for final planarization (high precision). This segmentation allows each process to optimize for its specific function without compromising the other.
Solution Approach 2:
Different regions of the substrate receive different treatments: mechanical grinding provides rough removal across the entire substrate, while CMP provides precise planarization specifically at the surface level where subsequent processing requires high flatness.
3Manufacturing precision
If wet etching is used to remove substrate, then selective removal is improved, but process time deteriorates
Solution Approach 1:
The etching process is segmented into mechanical grinding for bulk removal (fast but less selective) followed by wet etching for selective removal (slower but highly selective). This segmentation reduces the overall time required while maintaining selectivity for the final critical dimensions.
Solution Approach 2:
Mechanical grinding performs excessive removal of substrate material beyond the final required thickness, which is then precisely corrected by the selective wet etching process. This partial action approach trades some material removal time for enhanced selectivity and precision in the final substrate thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enables effective removal of the semiconductor substrate, allowing for the formation of shorter, higher-density backside vias and interconnect layers, enhancing the accessibility and connectivity of the IC device layers.
Implementation Method 1
A first portion of the semiconductor substrate may be removed by mechanical grinding
Implementation Method 2
a second portion of the semiconductor substrate may be removed by wet etch
Implementation Method 3
The remaining portion of the semiconductor substrate may be removed by chemical mechanical planarization (CMP) using a selective slurry
Data Source
AI summary
Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.