Backside Signal Routing Layout to Cut IC RC Delay
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Solution Overview
Problem
As integrated circuit (IC) device densities increase, the decreasing sizes of conductive lines lead to increased RC delays, negatively impacting performance due to higher impedance in signal transmission.
Innovation Solution
Implementing backside signal routing using wider or multiple backside conductive paths to reduce overall impedance and improve IC device performance, by connecting frontside signal paths to backside conductive layers through conductive pillars and vias, thereby optimizing signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device density is increased to improve integration, then transistor count increases, but conductive line sizes decrease leading to increased RC delays
Solution Approach 1:
The patent introduces a third dimension by routing conductive lines through the substrate thickness direction, creating via structures that connect front surface devices to back surface interconnects. This vertical routing dimension allows signal paths to bypass the planar congestion on the front surface, effectively increasing the available routing space and reducing RC delays despite high device density.
Solution Approach 2:
The conductive interconnect structure is segmented into multiple layers and surfaces: front surface contact regions, vertical via structures, and back surface conductive lines. This segmentation allows each segment to be optimized independently - front surface contacts are minimized, via structures provide direct vertical paths, and back surface lines can be made wider and shorter, collectively reducing the overall RC delay.
2Quantity of substance
If conductive line size is decreased to accommodate higher density, then more devices fit on chip, but signal transmission impedance increases
Solution Approach 1:
By moving the wide-trace interconnect layer to the back surface of the substrate, the patent creates a separate dimension for high-current signal routing. This allows the front surface to maintain high device density with small contacts, while the back surface provides low-impedance return paths through wider conductive lines, thus maintaining signal transmission quality despite reduced front surface line sizes.
Solution Approach 2:
Different regions of the conductive interconnect system are given different properties: front surface contacts are small and numerous for device integration, while back surface conductive lines are wide and sparse for low-impedance signal transmission. This local differentiation of conductive line properties allows each region to be optimized for its specific function while working together to solve the overall density-impedance contradiction.
Data Source
AI summary
In some embodiments, an integrated circuit device includes a substrate having a frontside and a backside; one or more active semiconductor devices formed on the frontside of the substrate; conductive paths formed on the frontside of the substrate; and conductive paths formed on the backside of the substrate. At least some of the conductive paths formed on the backside of the substrate, and as least some of the conductive paths formed on the front side of the substrate, are signal paths among the active semiconductor devices. In in some embodiments, other conductive paths formed on the backside of the substrate are power grid lines for powering at least some of the active semiconductor devices.