Backside Routing Layout for Lower-Density Semiconductor Interconnects
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area through reduced minimum feature sizes, the challenge of managing increased routing density and improving routing performance becomes critical.
Innovation Solution
The implementation of backside routing for power supply lines, electrical ground lines, and signaling in semiconductor devices, reducing the total routing required on the front-side interconnect structure by utilizing a backside interconnect structure for connectivity to front-side devices such as transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but routing density increases and routing performance deteriorates
Solution Approach 1:
The patent introduces backside routing as a new dimension for interconnect paths. By utilizing the backside of the semiconductor device substrate, routing paths are extended from a single-plane (front-side only) configuration to a multi-plane configuration. This dimensional expansion allows routing traffic to be distributed across front-side and back-side interconnect structures, thereby reducing routing density on the front-side while maintaining high integration density of components.
2Ease of operation
If all routing is performed on the front-side interconnect structure, then connectivity to front-side devices is achieved, but routing density increases and routing performance decreases
Solution Approach 1:
The patent segments the routing function into front-side routing and backside routing. The front-side interconnect structure handles routing to front-side devices, while the backside interconnect structure handles routing to backside devices. This segmentation distributes the routing load across two separate interconnect structures, reducing the routing density burden on the front-side while maintaining comprehensive connectivity to all devices on both sides of the substrate.
Data Source
AI summary
In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.