Backside Routing Structure for Dense Semiconductor Interconnects
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, the increasing complexity of routing for power supply lines, electrical ground lines, and signaling poses challenges in reducing routing density and improving performance on the front-side interconnect structure, leading to inefficiencies in connectivity and potential parasitic capacitance issues.
Innovation Solution
The implementation of a backside interconnect structure that routes power supply lines, electrical ground lines, and signaling on the backside of a semiconductor chip, reducing the need for front-side routing and enhancing connectivity by separating signal and power regions, thereby minimizing parasitic capacitance and increasing routing density and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If routing is performed on the front-side interconnect structure, then connectivity is achieved, but routing density increases and parasitic capacitance occurs
Solution Approach 1:
The patent applies backside routing to move interconnect structures from the traditional front-side plane to the backside of the semiconductor device, effectively utilizing the third dimension (depth/thickness) of the device structure. This dimensional transition separates signal routing from power supply routing, reducing routing density on the front side while maintaining necessary connectivity.
2Reliability
If routing is performed on the front-side interconnect structure, then connectivity is achieved, but parasitic capacitance increases
Solution Approach 1:
The patent segments the interconnect structure into separate functional regions: signal routing is performed on the front side while power supply routing is performed on the backside. This segmentation separates adjacent signal and power lines that would otherwise be in close proximity on the same layer, thereby reducing parasitic capacitance between these conductors while maintaining their respective connectivity functions.
3Productivity
If feature size is reduced to increase integration density, then more components are integrated, but routing complexity increases
Solution Approach 1:
By utilizing backside routing, the patent effectively doubles the available routing space by using both the front and back surfaces of the semiconductor device. This dimensional expansion allows for more complex routing patterns and higher integration density without proportionally increasing routing complexity on any single layer, as power and signal routing are distributed across different surfaces.
Data Source
AI summary
In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.