Backside Source/Drain Contact Structure for Scaled GAA Transistors
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Solution Overview
Problem
Existing gate-all-around (GAA) transistors face challenges in scaling down critical poly pitch and critical dimension of backside source/drain contacts, leading to increased resistance and the need for precise overlay control, which complicates manufacturing.
Innovation Solution
A novel structure and fabrication method involving the formation of backside source/drain contacts by creating first and second openings to expose semiconductor material layers, allowing for reduced resistance and mitigating overlay control requirements, using selective etching and deposition processes to form conductive connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If critical poly pitch and critical dimension of backside source/drain contacts are scaled down, then device density and integration are improved, but resistance increases and manufacturing precision requirements become more stringent
Solution Approach 1:
The patent performs preliminary actions by forming the first opening to expose the semiconductor material layer and creating the sidewall dielectric layer before forming the second opening. This preliminary structuring establishes precise alignment references that mitigate overlay control requirements during subsequent processing steps, allowing scaling without proportionally increasing precision demands.
Solution Approach 2:
The patent introduces a sidewall dielectric layer as an intermediary structure between the semiconductor material layer and the backside source/drain contact. This intermediary element facilitates precise positioning and alignment, serving as a physical reference that reduces the stringency of overlay control requirements while enabling continued scaling.
2Area of moving object
If critical poly pitch and critical dimension are scaled down, then device density is improved, but resistance of backside source/drain contacts increases
Solution Approach 1:
The patent transitions from planar contact geometry to a three-dimensional structure by forming openings that extend through multiple layers and creating sidewall dielectric layers. This dimensional change allows the contact structure to maintain lower resistance through optimized vertical and lateral pathways while accommodating scaled-down device dimensions.
Solution Approach 2:
The patent applies local quality by forming a sidewall dielectric layer specifically at the interfaces where conductivity is critical, while leaving other regions with different material properties. This localized structural optimization reduces resistance at key contact points without requiring uniform changes across the entire device structure.
3Reliability
If existing GAA transistor structures are used, then gate control is achieved, but manufacturing complexity and overlay control requirements increase
Solution Approach 1:
The patent segments the contact formation process into distinct stages: forming a first opening to expose the semiconductor material layer, creating a sidewall dielectric layer, and then forming a second opening. This segmentation breaks down the complex manufacturing process into manageable steps with clearer alignment requirements, reducing overall process complexity while maintaining gate control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces resistance in backside source/drain contacts and enhances manufacturing efficiency by utilizing the space occupied by semiconductor material layers, ensuring reliable connections without short-circuits and improving overlay control.
Implementation Method 1
creating first and second openings to expose semiconductor material layers
Implementation Method 2
using selective etching and deposition processes to form conductive connections
Data Source
AI summary
A method of forming a semiconductor structure includes forming a fin structure; forming first and second source/drain trenches in the fin structure; forming first and second semiconductor material layers in the first and second source/drain trenches, respectively; and forming first and second source/drain features over the first and second semiconductor material layers in the first and second source/drain trenches, respectively. The method further includes flipping the semiconductor structure; forming a hard mask layer on a backside of the substrate; etching the hard mask layer and the substrate to form a first opening that exposes the first semiconductor material layer; forming an insulating layer on a sidewall of the first opening; removing the first semiconductor material layer to form a second opening that exposes the first source/drain feature; and depositing a conductive material in the first and second openings to form a first source/drain contact.