Backside Power Rail Contact Scheme for Lower S/D Resistance
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Solution Overview
Problem
As semiconductor integrated circuits continue to scale down, existing methods for forming power rails and vias on the backside of ICs fail to adequately reduce resistance and coupling capacitance, leading to increased voltage drop and power consumption.
Innovation Solution
The formation of a sacrificial contact via on the backside of the wafer before channel structures are formed, which is later replaced by a conductive contact via, allowing for a larger contact area between source/drain epitaxial features and backside power rails, thereby reducing contact resistance and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power rails are formed above the transistors using conventional methods, then the fabrication process is simple, but the resistance is high and voltage drop increases
Solution Approach 1:
The patent inverts the conventional power rail formation approach by forming power rails on the backside of the substrate rather than above the transistors. This inversion allows power rails to be created before transistor fabrication, enabling lower resistance paths and reduced voltage drop while maintaining compatibility with standard CMOS processes.
Solution Approach 2:
The patent performs preliminary action by forming power rails and contact vias on the backside of the substrate before the transistor fabrication process begins. This advance preparation establishes low-resistance power distribution paths early in the process, preventing voltage drop issues that would otherwise require complex remedial measures later.
2Reliability
If contact area between source/drain and power rails is minimized, then the device footprint is small, but the contact resistance is high
Solution Approach 1:
The patent moves the power rail contact interface from the vertical dimension (above transistors) to the horizontal dimension (backside of substrate). This dimensional change allows for expanded contact area between source/drain regions and power rails without increasing the device footprint, thereby reducing contact resistance effectively.
3Productivity
If more metal tracks are used to increase gate density, then the device performance improves, but the fabrication complexity increases
Solution Approach 1:
The patent segments the power distribution function by creating separate power rail layers on the backside of the substrate, distinct from the signal interconnect layers on the frontside. This segmentation allows independent optimization of power delivery and signal routing, enabling increased gate density without proportionally increasing overall fabrication complexity.
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.