Self-Aligned Backside Source/Drain Contacts for Overlay Control
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Solution Overview
Problem
Existing techniques for forming source/drain contacts and connections to power rails in multi-gate devices, such as FinFETs and GAA transistors, face challenges in achieving the required device density, cell isolation, and performance as the scale of devices decreases, leading to increased resistance due to smaller feature areas.
Innovation Solution
A self-aligned backside contact formation scheme is employed, which provides a larger contact area and improves overlay and critical dimension control, allowing for lower resistance and enhanced device performance by forming contacts to a power rail disposed along the backside of the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional contact formation techniques are used to reduce contact landing size for scaling, then device density improves, but contact resistance increases and device performance deteriorates
Solution Approach 1:
The patent transitions from planar contact formation to three-dimensional contact structures that extend vertically through the substrate thickness. Contacts are formed as vias penetrating the substrate from front surface to back surface, enabling contact area expansion in the vertical dimension while maintaining small lateral footprint, thus achieving both high device density and low contact resistance
Solution Approach 2:
The contact structure is nested within the substrate thickness, with contacts formed as through-substrate vias that pass through the entire substrate. This nesting approach allows the contact to occupy the vertical space within the substrate, effectively increasing contact area without increasing lateral dimensions, thereby resolving the contradiction between device density and contact resistance
2Quantity of substance
If contact landing size is reduced to increase device density, then more devices can be packed, but overlay and critical dimension control become more difficult
Solution Approach 1:
By moving the contact formation problem into the vertical dimension through through-substrate via formation, the patent reduces sensitivity to lateral overlay errors. The via alignment can be achieved with relaxed lateral tolerances compared to traditional planar contacts, as the via structure extends vertically providing a more robust alignment target that is less sensitive to small lateral misalignments
Solution Approach 2:
The patent introduces intermediate structures including mandrels and spacers that facilitate precise via formation. These intermediary elements serve as alignment references and process control features that improve critical dimension control during the via formation process, enabling accurate contact placement even at reduced dimensions
3Productivity
If existing contact reduction schemes are implemented, then some scaling benefits are achieved, but the required level of device density and cell isolation is not met
Solution Approach 1:
The through-substrate via contact structure enables superior space utilization by exploiting the vertical dimension within the substrate. This approach achieves higher device density compared to planar contact reduction schemes, as contacts can be formed directly beneath active devices without requiring additional lateral spacing, thereby meeting the required density levels while maintaining production efficiency
Solution Approach 2:
The patent employs preliminary patterning steps including mandrel formation and spacer deposition that pre-establish the contact locations and dimensions. These preliminary actions enable precise contact formation in subsequent steps, achieving the required device density and cell isolation without compromising production efficiency through a well-sequenced manufacturing process
Data Source
AI summary
A method of forming a semiconductor including forming a source/drain feature adjacent to a semiconductor layer stack disposed over a substrate. The method further includes forming a dummy fin adjacent to the source/drain feature and adjacent to the semiconductor layer stack. The method further includes performing an etching process from a backside of the substrate to remove a first portion of the dummy fin adjacent to the source/drain feature, thereby forming a first trench in the dummy fin, where the first trench extends from the dummy fin to the source/drain feature. The method further includes forming a first dielectric layer in the first trench and replacing a second portion of the dummy fin with a source/drain contact.