Backside Source/Drain Via Structure for Lower Contact Resistance
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Solution Overview
Problem
Conventional integrated circuits (ICs) face increased voltage drop and power consumption due to the scaling down of power rails, necessitating improved methods for forming power rails and vias on the backside of ICs to reduce resistance and enhance performance.
Innovation Solution
The implementation of backside power rails and vias with expanded dimensions, specifically without a dielectric liner, to increase volume and interfacial area, combined with a method that includes selective etching and lateral expansion of via holes to reduce resistance and enhance device integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If power rails are scaled down to maintain integration density, then device integration density is improved, but voltage drop and power consumption increase
Solution Approach 1:
The patent introduces backside power rails and vias, utilizing the third dimension (vertical depth from backside to frontside) to create additional current paths. By forming via holes through the substrate and filling them with conductive material, the invention adds vertical conductive pathways that complement the lateral power rails, effectively distributing current in 3D space rather than being constrained to 2D planes, thereby reducing resistance and power consumption while maintaining integration density.
2Ease of manufacture
If conventional via structures with dielectric liners are used, then manufacturing process is simplified, but contact resistance is high due to limited interfacial area
Solution Approach 1:
The invention changes the geometric parameters of the via structure by laterally expanding the via holes beyond the original fin width. This expansion increases the cross-sectional area and interfacial contact area between the conductive fill material and the surrounding structures, thereby reducing contact resistance. The lateral expansion is achieved through selective etching and filling processes that modify the via dimensions while maintaining manufacturing feasibility.
3Reliability
If via hole dimensions are increased to reduce resistance, then contact resistance decreases, but manufacturing precision requirements increase
Solution Approach 1:
The invention performs preliminary actions by forming mandrels and applying sacrificial layers before creating the final via structure. The mandrels are formed with controlled dimensions, and sacrificial layers are deposited to define the final via geometry. These preliminary structures serve as templates that guide subsequent etching and filling processes, ensuring that the final via holes achieve the desired expanded dimensions with appropriate precision without requiring direct high-precision formation of the final via structure.
Data Source
AI summary
A semiconductor structure includes a power rail; an isolation structure over the power rail; first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature; one or more channel layers over the isolation structure and connecting the first and the second S/D features; a first via structure extending through the isolation structure and electrically connecting the first S/D feature and the power rail; and a first dielectric feature extending through the isolation structure and physically contacting the second S/D feature and the power rail. The first via structure has a first width in a first cross-section perpendicular to the first direction, the first dielectric feature has a second width in a second cross-section parallel to the first cross-section, and the first width is greater than the second width.


