Backside Self-Aligned Conductive Via Bar for Sub-10nm ICs
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Solution Overview
Problem
The challenge in integrated circuit fabrication lies in maintaining mobility and short channel control as microelectronic device dimensions scale below the 10 nanometer node, particularly in forming conductive deep via bars in narrow, high aspect ratio trenches, where conventional methods face difficulties in achieving precise alignment and filling without compromising lithographic processes.
Innovation Solution
The implementation of backside self-aligned conductive via bars using sub-fins with a guide spacer for patterning, which allows for the elimination of an immersion lithography pass and provides a self-aligned conductive deep via bar process, enabling co-planarity with sub-fins and trench contact structures without the need for precise front-side alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional lithographic processes are used to pattern features at smaller dimensions, then the critical dimension can be reduced, but the spacing between features becomes insufficient
Solution Approach 1:
The patent performs via bar patterning from the backside of the substrate rather than the frontside. This inversion of the patterning direction allows the via bars to be self-aligned to the trench contact structures without requiring additional lithographic alignment, effectively decoupling the critical dimension control from the spacing requirements
Solution Approach 2:
The via bars are formed to be self-aligned to the trench contact structures through the backside patterning process. The guide spacer and etch alignment automatically position the via bars relative to the trench contacts without requiring additional lithographic steps or alignment procedures, allowing the structures to define their own positions
2Measurement precision
If immersion lithography is used to achieve precise alignment, then alignment precision improves, but the complexity of the lithographic process increases
Solution Approach 1:
The via bars are formed to be self-aligned to the trench contact structures through the backside patterning process. The guide spacer and etch alignment automatically position the via bars relative to the trench contacts without requiring additional lithographic steps or alignment procedures, allowing the structures to define their own positions
Solution Approach 2:
The patent performs via bar patterning from the backside of the substrate rather than the frontside. This inversion of the patterning direction allows the via bars to be self-aligned to the trench contact structures without requiring additional lithographic alignment, effectively decoupling the critical dimension control from the spacing requirements
3Productivity
If conductive via bars are formed in narrow, high aspect ratio trenches, then the device density increases, but the manufacturing difficulty increases
Solution Approach 1:
The patent performs via bar patterning from the backside of the substrate rather than the frontside. This inversion of the patterning direction allows the via bars to be self-aligned to the trench contact structures without requiring additional lithographic alignment, effectively decoupling the critical dimension control from the spacing requirements
Solution Approach 2:
The via bars are formed to be self-aligned to the trench contact structures through the backside patterning process. The guide spacer and etch alignment automatically position the via bars relative to the trench contacts without requiring additional lithographic steps or alignment procedures, allowing the structures to define their own positions
Data Source
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AI summary
Integrated circuit structures having backside self-aligned conductive via bars, and methods of fabricating integrated circuit structures having backside self-aligned conductive via bars, are described. For example, an integrated circuit structure includes a first sub-fin structure over a first stack of nanowires. A second sub-fin structure is over a second stack of nanowires. A first gate electrode is around the first stack of nanowires. A second gate electrode is around the second stack of nanowires. A conductive trench contact structure is between the first gate electrode and the second gate electrode. A conductive via bar is on the conductive trench contact structure, the conductive via bar having a backside surface co-planar with a backside surface of the first and second sub-fin structures.