Backside Self-Aligned Power Rails for Dense GAA Semiconductor Devices
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Solution Overview
Problem
Conventional power rail schemes in gate-all-around (GAA) devices face challenges such as low density, high resistance, and short circuits due to process limitations, affecting semiconductor device performance.
Innovation Solution
A self-aligned backside power rail scheme is implemented, utilizing a bottom dielectric layer to control via positioning, preventing short circuits between the metal gate and source/drain regions by ensuring power rail vias connect only to the source region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional power rail schemes are used in GAA devices, then power lines can be formed on the backside of the substrate, but the density is low and resistance is high due to process limitations
Solution Approach 1:
A bottom dielectric layer is introduced as an intermediary element between the substrate and the power rail vias. This dielectric layer enables self-aligned via formation, where the via positioning is automatically controlled by the dielectric layer's physical structure, thereby achieving high manufacturing precision and power rail density without requiring additional alignment processes
2Reliability
If conventional power rail schemes are used, then power lines can be formed on the backside, but isolation between the metal gate and the power line is very challenged
Solution Approach 1:
The bottom dielectric layer serves as a mediator that physically separates and isolates the metal gate from the power line. By positioning the power rail vias to connect only to the source region through this dielectric layer, automatic electrical isolation is achieved without requiring complex additional isolation structures
Solution Approach 2:
The harmful electrical connection between the metal gate and power line is extracted or removed by designing the via structure to connect exclusively to the source region. This extraction of the unwanted conductive path achieves isolation while simplifying the overall device structure
3Reliability
If conventional power rail schemes are used, then power lines can be formed on the backside, but short issues from the source region to the drain region may occur
Solution Approach 1:
The via positioning is made self-aligning through the bottom dielectric layer, which automatically guides the via formation process to connect only to the source region. This self-service mechanism prevents short circuits between source and drain regions without requiring complex external alignment controls or additional process steps
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.