Backside Self-Aligned Silicide for Lower-Resistance Epi Contacts
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Solution Overview
Problem
Existing trench silicide processes for advanced transistor technologies, such as FinFET and gate-all-around FETs, face challenges with higher contact resistance due to smaller contact areas and unreacted metal residues, complicating the formation of low-resistance contacts.
Innovation Solution
Implementing a self-aligned silicide process that forms silicide layers on the bottom surfaces of epi layers without the need for masking, ensuring a larger contact area and removing unreacted metal, thereby reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If trench silicide process is used, then contact area is reduced for advanced transistor scaling, but contact resistance increases and unreacted metal residues remain
Solution Approach 1:
The silicide formation process is made self-aligned by using the epi layer itself as the mask. The metal layer is deposited over the entire backside surface including the epi layer bottom surface, and during annealing, the metal automatically reacts with silicon only where needed to form silicide, while unreacted metal is subsequently removed. This self-service mechanism eliminates the need for separate masking steps and ensures complete reaction without residues.
Solution Approach 2:
Instead of forming silicide only in trenches (conventional approach), the invention inverts the approach by depositing metal over the entire backside surface and then selectively removing unreacted metal. This inversion allows the silicide to form on the full contact area including regions that would traditionally be masked, thereby maximizing contact area while ensuring complete reaction.
2Ease of manufacture
If trench silicide process is used, then manufacturing complexity increases due to masking requirements, but contact area is limited
Solution Approach 1:
The epi layer serves as its own mask during silicide formation. The metal layer is deposited conformally over the backside surface, and during annealing, silicon from the epi layer diffuses into the metal to form silicide automatically at the interface. This self-service mechanism eliminates complex photolithography masking steps while ensuring silicide forms precisely where the epi layer is present, maximizing contact area.
Solution Approach 2:
The invention extracts and removes only the unreacted metal portion after annealing, leaving behind the fully reacted silicide layer. This selective removal approach simplifies the manufacturing process by eliminating multiple masking and patterning steps, while ensuring that the silicide contact area matches the epi layer footprint exactly.
3Area of stationary object
If self-aligned silicide process is implemented, then contact area is increased, but additional processing steps are required
Solution Approach 1:
The invention merges the silicide formation step with the backside contact formation process. By depositing the metal layer that serves dual purposes as both the silicide source and the backside contact material, and performing a single annealing step that simultaneously forms the silicide and prepares the contact, the process reduces overall complexity despite the self-aligned approach.
Solution Approach 2:
The epi layer automatically serves as the mask during silicide formation, eliminating the need for separate masking layers and lithography steps. The metal layer self-organizes during annealing to react with silicon only where the epi layer is present, and subsequent removal of unreacted metal is a simple single step. This self-service mechanism actually reduces processing complexity compared to conventional trench silicide with multiple masking steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The self-aligned silicide process achieves lower contact resistance and improved contact integrity by covering a larger surface area and eliminating unreacted metal residues, enhancing the performance of backside contacts in advanced transistor technologies.
Implementation Method 1
heating the chip, wherein the heating causes the metal layer to react with silicon in the first epi layer to form a first silicide layer and react with silicon in the second epi layer to form a second silicide layer
Data Source
AI summary
The chip includes a first epitaxial (epi) layer, a second epi layer, a gate between the first epi layer and the second epi layer, and one or more channels coupled between the first epi layer and the second epi layer, wherein the one or more channels pass through the gate. The chip also includes a first salicide layer formed on a bottom surface of the first epi layer.