Backside-Coupled Semiconductor Isolation Structure for Larger Active Regions

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Solution Overview

Problem

Existing semiconductor device structures require additional areas for conductive traces to transmit supply voltage to doped regions, which reduces the size of active regions and affects performance.

Innovation Solution

A semiconductor device structure with a doped region configured to generate a PN junction for electrical isolation, where a conductive feature extends from the backside surface to couple with the doped region, allowing for increased active region size by transmitting voltage from the backside surface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conductive traces are added on the active surface to transmit supply voltage to doped regions, then electrical coupling is achieved, but the active region area is reduced

Engineering Contradiction:
Improveelectrical couplingVSAvoidactive region area
Core Design Contradiction:
ReliabilityVSArea of moving object

Solution Approach 1:

The patent introduces a vertical conductive feature extending from the backside surface through the substrate to reach the doped region, transforming the horizontal trace routing problem into a vertical connection solution. This dimensional change eliminates the need for surface traces while maintaining electrical coupling.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Instead of routing conductive traces from the front active surface to the doped region, the patent inverts the approach by providing electrical coupling from the backside surface of the substrate, reversing the conventional direction of voltage transmission.

Inventive Principle:
Principle #13The other way round (Inversion)

2Use of energy by moving object

If additional conductive traces are placed on the active surface, then voltage transmission is enabled, but device performance is adversely affected

Engineering Contradiction:
Improvevoltage transmissionVSAvoiddevice performance
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The conductive feature is positioned vertically from the backside surface, removing it from the active surface plane where it would interfere with device performance. This spatial separation allows voltage transmission without compromising productivity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If conductive traces are extended to reach doped regions, then electrical isolation is achieved, but the layout area increases

Engineering Contradiction:
Improveelectrical isolationVSAvoidlayout area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent inverts the conventional approach by forming the doped region first and then providing vertical electrical coupling from the backside, rather than extending horizontal traces from the surface. This inversion minimizes layout area while achieving electrical isolation.

Inventive Principle:
Principle #13The other way round (Inversion)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration increases the size of active regions, thereby improving the performance of the semiconductor device structure by reducing the need for additional areas on the active surface for conductive traces.

Implementation Method 1

The first doped region includes a second conductive type different from the first conductive type. The first doped region is disposed between the first gate structure and the second gate structure.

Methodology Applied
Scientific EffectPN junction:

Implementation Method 2

The first conductive feature extends between the first surface of the first substrate and the first doped region.

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS12062656B2Semiconductor device structure
Publication Date: 2024.08.13 NAN YA TECH
  • US12062656B2 patent drawing
  • US12062656B2 patent drawing
  • US12062656B2 patent drawing

AI summary

A semiconductor device structure including a doped region under an isolation feature is provided. The semiconductor device structure includes a first substrate, a first well region, a first gate structure, a second gate structure, a first doped region, and a first conductive feature. The substrate has a first surface and a second surface opposite to the first surface. The first well region is in the first substrate. The first well region has a first conductive type. The first gate structure is disposed on the second surface. The second gate structure is disposed on the second surface. The first doped region includes a second conductive type different from the first conductive type. The first doped region is disposed between the first gate structure and the second gate structure. The first conductive feature extends between the first surface of the first substrate and the first doped region.