Backside Semiconductor Layout for Lower Parasitic Routing
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Solution Overview
Problem
The scaling down of semiconductor devices increases complexity in electrical routing and placement of components, leading to challenges such as increased resistance and capacitance due to larger active or passive components occupying precious real estate and requiring multiple metallization layers.
Innovation Solution
Implementing passive and active components on the backside of a substrate while front-end-of-line devices are fabricated on the front side, using selective deep ion-implantation processes to form an ion implantation profile, allowing for relaxed footprint and reduced parasitic resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If larger active or passive components are placed in frontside interconnect structure, then component functionality is achieved, but footprint area increases and resistance increases
Solution Approach 1:
The patent moves passive components from the frontside interconnect structure to the backside of the substrate, utilizing the third dimension (substrate thickness) to resolve the area conflict. This allows the frontside to maintain small footprint while the backside accommodates larger component structures without increasing overall device area.
Solution Approach 2:
Instead of placing components on the conventional frontside, the patent inverts the arrangement by placing passive components on the backside of the substrate. This inversion resolves the contradiction by allowing larger component footprints on the backside while maintaining compact frontside interconnect structures.
2Reliability
If larger active or passive components are placed in frontside interconnect structure, then component functionality is achieved, but capacitance increases
Solution Approach 1:
By relocating passive components to the backside, the patent reduces the overlap area between signal lines and component electrodes on the frontside, thereby reducing parasitic capacitance while maintaining component functionality.
Solution Approach 2:
The patent extracts passive components from the frontside interconnect structure and places them on the backside, separating the signal routing layer from the passive component layer to minimize parasitic coupling and capacitance effects.
3Productivity
If scaling down process is used, then production efficiency increases and costs decrease, but device complexity increases
Solution Approach 1:
The patent segments the device into frontside active components and backside passive components, allowing independent optimization of each section. This segmentation simplifies the processing complexity by enabling separate fabrication flows for active and passive components while maintaining high production efficiency through standard scaling processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves performance and reliability by reducing parasitic resistance and capacitance, enhancing energy efficiency and memory retention.
Implementation Method 1
performing an ion implantation process to a substrate to form a doped region
Data Source
AI summary
Device structures and methods of forming the same are provided. A device structure according to the present disclosure includes a substrate having a front side and a back side, a fin structure over the front side, a plurality of nanostructures disposed over the fin structure, a gate structure wrapping around each of the plurality of nanostructures, a first doped region disposed over the back side of the substrate, a backside dielectric layer over the first doped region, and a first contact feature extending through the backside dielectric layer to interface the first doped region.