Back-Illuminated Image Sensor Wafer Bonding Without Deep Vias
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Solution Overview
Problem
The existing methods for manufacturing semiconductor devices, such as solid-state imaging devices, face challenges in forming high-aspect ratio connection holes in substrates, which are costly and complicated, limiting the use of connection conductor materials and hindering mass production and cost reduction.
Innovation Solution
A method involving bonding half-finished semiconductor wafers with pixel arrays and logic circuits, thinning the wafers, and forming electric connections between them, allowing for the use of optimal process technologies to create high-performance semiconductor devices with reduced production costs and increased productivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connection holes are formed in substrates to connect image sensor chip and logic circuit chip, then electrical connection between chips is achieved, but the process becomes costly and complicated due to high aspect ratio requirements
Solution Approach 1:
The patent applies preliminary action by forming connection holes in the substrate before mounting the image sensor chip and logic circuit chip. This allows the holes to be created when the substrate is still relatively thin, avoiding the need to drill through fully assembled chip stacks. The connection conductors are also preliminarily formed in these holes before chip mounting, simplifying the overall manufacturing process while ensuring reliable electrical connections between chips.
2Reliability
If connection holes are formed in substrates, then electrical connection is achieved, but conductor material selection is limited and costs increase
Solution Approach 1:
The connection conductors are formed in the connection holes before the image sensor chip and logic circuit chip are mounted on the substrate. This preliminary formation allows for the use of various conductor materials such as tungsten, copper, or aluminum without the constraints of post-assembly drilling. The preliminary timing enables material selection based on electrical performance requirements rather than manufacturing convenience, expanding material versatility while controlling costs.
3Adaptability or versatility
If separate chips are used for image sensor and logic circuit, then functional optimization is achieved, but device complexity and production cost increase
Solution Approach 1:
The patent merges the image sensor chip, logic circuit chip, and substrate into a single integrated device package. The substrate serves as both the mounting platform and the interconnection medium, combining multiple functions into one structure. This merging approach maintains the functional optimization benefits of separate chips while reducing overall device complexity by integrating the substrate as a common platform for both chips and their interconnections.
4Adaptability or versatility
If separate chips are mounted on substrate, then functional optimization is achieved, but mass production efficiency decreases
Solution Approach 1:
The connection holes and connection conductors are formed in the substrate before any chips are mounted. This preliminary preparation enables subsequent chip mounting and wire bonding to be performed in a streamlined sequence, facilitating mass production. The pre-formed connection structure eliminates the need for complex post-assembly drilling and conductor formation, significantly improving production efficiency while maintaining functional optimization through separate chips.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of high-performance semiconductor devices with efficient mass production and cost reduction by optimizing the formation of pixel arrays and logic circuits on separate wafers, facilitating the use of various connection conductor materials and simplifying the manufacturing process.
Implementation Method 1
bonding a first semiconductor wafer with a pixel array in a half-finished product state and a second semiconductor wafer with a logic circuit in a half-finished product state together
Implementation Method 2
making the first semiconductor wafer into a thin film
Data Source
Figure 1
Figure 2A~2C
Figure 3
AI summary
A semiconductor device is provided as a back-illuminated solid-state imaging device. The device is manufactured by bonding a first semiconductor wafer with a pixel array in a half-finished product state and a second semiconductor wafer with a logic circuit in a half-finished product state together, making the first semiconductor wafer into a thin film, electrically connecting the pixel array and the logic circuit, making the pixel array and the logic circuit into a finished product state, and dividing the first semiconductor wafer and the second semiconductor being bonded together into microchips.