Backside Signal and Power Layout for Dense Semiconductor Cells
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Solution Overview
Problem
As semiconductor devices scale down, they interfere with each other and face challenges in forming connections to a backside power network, making it difficult to maintain effective power distribution and signal transmission.
Innovation Solution
The semiconductor device incorporates backside power rails and signal lines formed in the same plane across a circuit row, with via connections between source/drain contacts and backside signal lines, and backside power rails connected to source/drain, allowing for reduced cell size and increased wiring efficiency by utilizing multistage processing to form trenches, fill with conductive metal, and create interlayer dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If devices are scaled down and placed closer together, then device density is improved, but device interference increases and connection formation becomes more difficult
Solution Approach 1:
The patent moves power network connections from the frontside to the backside of the semiconductor device, utilizing the third dimension (vertical stacking) to resolve lateral interference issues. By forming backside power rails and signal lines on the opposite side of the substrate, the design enables closer device spacing without increasing lateral interference, as connections are routed through the substrate thickness rather than across the device plane.
2Productivity
If devices are scaled down and placed closer together, then device density is improved, but connection formation to backside power network becomes more difficult
Solution Approach 1:
The patent performs preliminary actions by forming the backside power rails and signal lines before final device assembly and interconnection. The multistage processing approach includes early formation of trenches, deposition of conductive metals, and creation of via structures that pre-establish connection pathways, making subsequent device integration simpler and more reliable despite scaled dimensions.
Solution Approach 2:
The patent segments the power network into distinct backside power rails and signal lines that are independently formed and positioned. This segmentation allows for optimized routing and connection strategies, where power delivery and signal transmission are handled by separate structures, simplifying the overall connection formation process in scaled devices.
3Device complexity
If backside power rails and signal lines are formed in the same plane, then wiring efficiency is improved and cell size is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent employs dynamic, multistage processing where the formation of backside power rails and signal lines occurs in sequential stages with flexible parameter adjustments. Each stage can be independently optimized and controlled, allowing the manufacturing process to adapt to the complex geometry of same-plane routing while maintaining manufacturing feasibility through progressive structure development.
Data Source
AI summary
According to the embodiment of the present invention, a semiconductor device includes a first nanodevice comprised of a plurality of first transistors and a second nanodevice comprised of a plurality of second transistors. The second nanodevice is located adjacent to and parallel to the first nanodevice along an x-axis. A first backside signal line and a second backside signal line are located at a cell boundary of the first nanodevice. A first gap exists between the first backside signal line and the second backside signal line.