Backside Signal Routing for Lower RC Delay in IC Interconnects

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Solution Overview

Problem

As integrated circuit (IC) device densities increase, the decreased sizes of conductive lines lead to increased RC time constants, negatively impacting IC device performance.

Innovation Solution

Implementing backside signal routing using wider or more numerous backside conductive paths to reduce overall impedance and improve IC device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If device density is increased in IC devices, then transistor count and integration are improved, but conductive line sizes decrease leading to increased RC time constants and performance degradation

Engineering Contradiction:
Improvedevice densityVSAvoidsignal transmission performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies dimensionality change by routing signals through the backside of the substrate instead of confining all routing to the frontside. This utilizes the third dimension (depth/substrate thickness) to create additional routing resources, allowing wider conductive paths that reduce RC time constants while maintaining high device density on the frontside.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent segments the signal routing function between frontside and backside of the substrate. Critical signals with timing requirements are routed through the backside using wider conductive paths, while less time-critical signals remain on the frontside. This segmentation allows optimization of different signal types through different routing dimensions.

Inventive Principle:
Principle #1Segmentation

2Productivity

If conductive line sizes are decreased to accommodate higher device density, then more transistors can be integrated, but RC time constants increase negatively impacting performance

Engineering Contradiction:
Improvetransistor integrationVSAvoidRC time constant
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

By moving time-critical signal routing to the backside dimension, the patent creates wider conductive paths without increasing frontside congestion. This dimensional transition reduces resistance and capacitance for critical signals, decreasing RC time constants while maintaining high transistor integration density on the frontside.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent applies different routing qualities to different signals: backside routing with wider conductive paths is applied locally to time-critical signals, while standard frontside routing is used for less time-critical signals. This local quality differentiation optimizes performance for critical paths without compromising overall integration density.

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If traditional frontside routing is used, then manufacturing process is simpler, but signal transmission impedance is higher reducing device performance

Engineering Contradiction:
Improverouting implementationVSAvoidsignal transmission impedance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent introduces backside routing as an additional dimension for signal transmission. This provides wider conductive paths that reduce impedance for critical signals while maintaining compatibility with existing frontside routing infrastructure, achieving a balance between manufacturing complexity and transmission performance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250192051A1Backside signal routing
Publication Date: 2025.06.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250192051A1 patent drawing
  • US20250192051A1 patent drawing
  • US20250192051A1 patent drawing

AI summary

In some embodiments, an integrated circuit device includes a substrate having a frontside and a backside; one or more active semiconductor devices formed on the frontside of the substrate; conductive paths formed on the frontside of the substrate; and conductive paths formed on the backside of the substrate. At least some of the conductive paths formed on the backside of the substrate, and as least some of the conductive paths formed on the front side of the substrate, are signal paths among the active semiconductor devices. In some embodiments, other conductive paths formed on the backside of the substrate are power grid lines for powering at least some of the active semiconductor devices.