Backside Source/Drain Silicide for Low-Resistance GAA Contacts
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area through reduced minimum feature sizes, challenges arise in reducing contact resistance and ensuring efficient electrical connections in transistors.
Innovation Solution
A method involving the formation of a Gate-All-Around (GAA) transistor with a backside connection structure, utilizing a solid phase epitaxy regrowth (SPER) process to amorphize and dope the source/drain regions, followed by annealing to recrystallize and increase dopant solubility, resulting in thicker silicide regions with reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but contact resistance increases and electrical connection efficiency deteriorates
Solution Approach 1:
The patent applies parameter changes by modifying the physical and chemical properties of the source/drain regions through controlled amorphization and recrystallization processes. By changing the crystalline structure parameters and dopant concentration parameters during SPER, the contact resistance is reduced while maintaining the scaled dimensions required for high integration density
Solution Approach 2:
The patent utilizes phase transitions by intentionally transforming the source/drain regions from crystalline to amorphous phase during implantation, then back to crystalline phase during SPER annealing. This phase transition process enables dopant activation and silicide formation that reduces contact resistance in miniaturized devices
2Ease of manufacture
If conventional doping methods are used in scaled devices, then manufacturing process remains simple, but dopant activation is insufficient and contact resistance remains high
Solution Approach 1:
The patent applies preliminary action by performing amorphization implantation before the SPER annealing process. This preliminary transformation of the source/drain region to amorphous phase creates conditions that enhance subsequent dopant activation during recrystallization, achieving better contact properties without adding complex process steps
Solution Approach 2:
The patent replaces conventional thermal diffusion doping with solid phase epitaxy regrowth mechanism. Instead of relying on simple thermal diffusion, the SPER process uses controlled crystallization from amorphous phase to achieve superior dopant activation and electrical properties
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces contact resistance and enhances electrical connectivity by increasing dopant activation and minimizing voids at the interface, leading to improved performance and efficiency in semiconductor devices.
Implementation Method 1
performing an amorphization implantation process through the contact opening to generate an amorphous region in the source/drain region
Implementation Method 2
performing an anneal process to recrystallize the amorphous region
Implementation Method 3
performing a doping implantation process to introduce a dopant into the source/drain region
Data Source
AI summary
A method includes forming a transistor over a semiconductor substrate, which includes forming a source/drain region through an epitaxy process. The method further includes performing a backside thinning process to thin the semiconductor substrate, etching the semiconductor substrate to form a contact opening, wherein a back surface of the source/drain region is exposed through the contact opening, performing an amorphization implantation process through the contact opening to generate an amorphous region in the source/drain region, and forming a silicide region on the source/drain region.