Backside Semiconductor Source Structure for 3D Memory Channel Contact
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in forming efficient backside semiconductor source structures that provide reliable electrical contact to vertical semiconductor channels, which affects the performance and reliability of memory devices.
Innovation Solution
A method and structure involving an alternating stack of insulating and electrically conductive layers on a planar semiconductor layer, with a memory opening fill structure and a backside semiconductor source structure that includes an epitaxial doped semiconductor portion aligned with a single crystalline semiconductor layer and a polycrystalline doped semiconductor portion on the vertical semiconductor channel, enabling effective contact and alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a backside semiconductor source structure is formed to contact vertical semiconductor channels, then electrical connectivity is improved, but manufacturing complexity increases due to the need for precise alignment and multi-layer integration
Solution Approach 1:
The backside semiconductor source structure is segmented into multiple functional layers: a first semiconductor layer formed on the substrate, a second semiconductor layer formed on the first layer, and a third semiconductor layer formed on the second layer. This segmentation allows each layer to be optimized independently for electrical contact while simplifying the overall manufacturing process through modular construction.
Solution Approach 2:
The semiconductor layers are formed in advance on the substrate backside before final device assembly. The first semiconductor layer is deposited and patterned, followed by the second and third layers, creating a pre-aligned multi-layer structure that ensures precise electrical contact with vertical channels without requiring complex post-assembly alignment steps.
2Adaptability or versatility
If an alternating stack of insulating and electrically conductive layers is used, then device functionality is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
Spacer layers are introduced as intermediary elements between the insulating and electrically conductive layers in the alternating stack. These spacers provide physical separation and alignment references, ensuring that each layer is positioned with the required precision relative to adjacent layers, thereby enabling complex device functionality while maintaining manufacturability.
Solution Approach 2:
The alternating stack incorporates regions with different material compositions and electrical properties at specific locations. Insulating layers provide electrical isolation in certain regions, while electrically conductive layers provide pathways in other regions, allowing the structure to perform multiple functions simultaneously with optimized local properties for each function.
3Ease of operation
If the carrier substrate is removed to access the backside surface, then backside contact formation is enabled, but structural stability decreases
Solution Approach 1:
A support structure is formed beforehand on the substrate backside before carrier removal. This support structure consists of a first support layer deposited on the substrate, followed by a second support layer formed on the first layer. These pre-formed support layers provide mechanical reinforcement and structural stability during and after carrier substrate removal, preventing damage to the delicate semiconductor layers while enabling backside access for contact formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the electrical contact and alignment between the backside semiconductor source structure and the vertical semiconductor channel, improving the performance and reliability of three-dimensional memory devices by providing a low resistance Ohmic contact and reliable electrical connectivity.
Implementation Method 1
a backside semiconductor source structure comprising a third semiconductor material and contacting the vertical semiconductor channel and the planar semiconductor layer
Implementation Method 2
an epitaxial doped semiconductor portion in contact with and in epitaxial alignment with a single crystalline structure of the single crystalline semiconductor layer
Data Source
AI summary
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located on a semiconductor layer, a memory opening vertically extending through the alternating stack and the semiconductor layer, a memory opening fill structure located in the memory opening and containing a memory film and a vertical semiconductor channel, and a backside semiconductor source structure including a doped semiconductor material. The backside semiconductor source structure may be polycrystalline or single crystalline.