Self-Aligned Backside Source Contact for Short-Circuit Prevention
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Solution Overview
Problem
Existing backside contact structures for multi-gate transistors face challenges in forming satisfactory backside power rails without causing short circuits due to overlay variations, particularly between the backside source contact and the gate structure.
Innovation Solution
A self-aligned backside contact structure is implemented, where a bottom self-aligned contact (SAC) dielectric layer covers the backsides of the source feature and the gate structure, allowing selective access to the source feature and enabling the formation of backside source contact openings without high overlay precision, using a method that includes forming fin-shaped structures, recessing source and drain regions, and depositing epitaxial layers to create source and drain features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional backside contact structures are used, then routing can be moved to the backside, but overlay variations cause short circuits between backside source contact and gate structure
Solution Approach 1:
A bottom self-aligned contact (SAC) dielectric layer is introduced as an intermediary between the backside source contact and the gate structure. This dielectric layer acts as a protective mediator that prevents direct contact and potential short circuits while still allowing the backside routing to function. The SAC dielectric layer is specifically positioned to cover the gate structure and extend to the source contact region, creating a controlled interface that enables routing flexibility without compromising reliability.
2Reliability
If high overlay precision is required for backside source contact openings, then short circuits can be prevented, but manufacturing complexity and cost increase
Solution Approach 1:
The bottom SAC dielectric layer is formed in advance before the backside source contact opening is created. This preliminary action establishes a pre-defined protective structure that automatically prevents short circuits regardless of overlay variations. By preparing the dielectric layer beforehand with appropriate coverage of the gate structure, the need for high overlay precision during subsequent contact opening formation is eliminated, simplifying the manufacturing process while maintaining reliability.
3Manufacturing precision
If the bottom SAC dielectric layer covers both source feature and gate structure, then self-aligned formation is enabled, but device structure becomes more complex
Solution Approach 1:
The bottom SAC dielectric layer is designed to serve multiple functions simultaneously: it provides electrical isolation between the source contact and gate structure, enables self-aligned formation of the backside source contact opening, and acts as a protective barrier against short circuits. By consolidating these multiple functions into a single dielectric layer structure, the patent achieves manufacturing precision benefits without proportionally increasing device complexity, as the same structure delivers multiple protective and alignment functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents short circuits and enhances process window and yield by allowing self-aligned formation of backside source contact openings, reducing the risk of defects and improving the reliability of backside contact formation.
Implementation Method 1
depositing an epitaxial layer over the source region and the substrate to form a source feature
Data Source
AI summary
A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.