Backside Source Contact Step Profile for Overlay-Tolerant Isolation
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Solution Overview
Problem
Conventional methods for forming backside contacts in semiconductor devices often result in electrical shorts between the gate structure and the backside contact due to imperfect overlay during photolithography, leading to reduced yield and performance issues.
Innovation Solution
A method involving the formation of a dummy epitaxial feature in the source/drain opening that extends into the substrate, allowing for self-aligned etching processes to create a backside contact opening, reducing the risk of gate-source/drain shorting through a two-step etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional photolithography methods are used to form backside contacts, then the manufacturing process is simple, but electrical shorts occur between gate structure and backside contact due to imperfect overlay
Solution Approach 1:
A dummy epitaxial feature is introduced as an intermediary element during the etching process. This dummy feature serves as a sacrificial placeholder that defines the etch termination point, preventing the etch from reaching the gate structure even when overlay is imperfect. The dummy feature is later removed after serving its protective function, thereby eliminating shorts while maintaining manufacturing simplicity.
Solution Approach 2:
The dummy epitaxial feature is formed in advance during the epitaxial growth stage, before the backside contact etching process. This preliminary action ensures that the protective structure is already in place to guide the subsequent etching process, preventing damage to the gate structure due to overlay misalignment.
2Ease of manufacture
If photolithography overlay is less than perfect, then manufacturing is easier, but the backside source contact may be shorted to the gate structure
Solution Approach 1:
The dummy epitaxial feature acts as a mediator between the photolithography pattern and the actual etch process. It provides a physical boundary that stops the etch before reaching the gate, compensating for overlay errors and maintaining electrical isolation reliability even when photolithography alignment is not perfect.
Solution Approach 2:
The dummy epitaxial feature provides a cushioning buffer zone between the intended contact area and the gate structure. This buffer absorbs the impact of overlay misalignment, preventing direct contact between the backside source contact and the gate structure, thereby maintaining reliability despite manufacturing tolerances.
3Reliability
If a two-step etching process with dummy epitaxial feature is used, then gate structure damage is minimized, but the manufacturing process becomes more complex
Solution Approach 1:
The dummy epitaxial feature serves as a self-aligned intermediary that simplifies the overall process control. Although it adds one formation step, it eliminates the need for extremely tight overlay control and multiple alignment steps, thereby reducing process complexity in terms of alignment precision requirements while protecting gate structure integrity.
Solution Approach 2:
The dummy epitaxial feature is self-aligned through the epitaxial growth process itself, eliminating the need for separate alignment and patterning steps that would increase complexity. The feature automatically positions itself relative to the channel structure, providing protection without requiring complex process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the yield by minimizing damage to the gate structure and preventing electrical shorts, thereby improving the reliability and performance of semiconductor devices.
Implementation Method 1
anisotropically etching the substrate to form a backside contact opening to expose the dummy epitaxial feature of the source feature, selectively and isotropically etching the dummy epitaxial feature
Data Source
AI summary
A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes an epitaxial source feature and an epitaxial drain feature, a vertical stack of channel members disposed over a backside dielectric layer, the vertical stack of channel members extending between the epitaxial source feature and the epitaxial drain feature along a direction, a gate structure wrapping around each of the vertical stack of channel members, and a backside source contact disposed in the backside dielectric layer. The backside source contact includes a top portion adjacent the epitaxial source feature and a bottom portion away from the epitaxial source feature. The top portion and the bottom portion includes a step width change along the direction.