Self-Aligned Backside Connections for Source/Drain Power Delivery
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges in efficiently providing power delivery to field-effect-transistors, particularly in achieving self-aligned backside connections to the source/drain epitaxy, which complicates the integration of backside power rails and increases resistance, affecting device performance and area utilization.
Innovation Solution
The method involves forming a backside power delivery network with self-aligned connections to the source/drain epitaxy, utilizing a pre-formed etch stop layer and selective removal of the BOX layer to expose the bottom of the source/drain epitaxy, allowing for direct contact and reduced complexity in patterning, thereby improving etch and fill aspect ratios and enabling merged power rails for reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional backside power delivery integration methods are used, then power delivery to field-effect-transistors is achieved, but the integration complexity increases and resistance increases
Solution Approach 1:
The patent applies preliminary action by forming the etch stop layer and defining the backside connection regions before completing the source/drain epitaxy growth. This allows the backside power delivery network to be self-aligned to the source/drain regions, eliminating the need for complex post-epitaxy alignment steps and reducing integration complexity while maintaining reliable power delivery
2Reliability
If conventional backside power delivery integration methods are used, then power delivery to field-effect-transistors is achieved, but device area increases
Solution Approach 1:
The patent merges the backside power delivery network with the source/drain epitaxy regions by creating self-aligned connections where the backside contacts directly connect to the source/drain regions. This consolidation eliminates separate power delivery structures and reduces the overall device footprint while maintaining effective power delivery to the transistors
3Manufacturing precision
If self-aligned backside connections are implemented, then manufacturing precision is improved, but fabrication process complexity increases
Solution Approach 1:
The patent implements self-service by designing the backside connection structure to be self-aligned through the etch stop layer and epitaxy growth process. The etch stop layer automatically defines the connection boundaries, and the epitaxy growth self-aligns to these boundaries, eliminating the need for complex external alignment procedures and making the high-precision fabrication inherently part of the material processing itself
Data Source
AI summary
Provided is a semiconductor device. The semiconductor device comprises a plurality of logic devices. The logic devices have frontside wiring. The semiconductor device further comprises a backside power delivery network (BSPDN). The semiconductor device further comprises a connection between the BSPDN and the bottom of a source/drain epitaxy of a logic device. The connection is self-aligned on at least two sides.