Backside Source/Drain Contacts for Dense Transistor Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to shrink in size, manufacturing defects and integration challenges arise, particularly in forming reliable source/drain contacts for transistors, which affect the performance and yield of semiconductor devices.
Innovation Solution
A method is introduced where a majority of the semiconductor substrate is etched away, leaving a portion to cover the edge regions of the source/drain regions, forming backside contacts to protect them during the manufacturing process, thereby reducing defects and improving the integration density of transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but manufacturing defects and integration challenges increase
Solution Approach 1:
The patent applies preliminary action by forming a protective layer over the source/drain regions before etching the semiconductor substrate. This protective layer is deposited in advance to prevent damage to the source/drain regions during subsequent substrate removal, thereby addressing manufacturing defects that arise from miniaturization while maintaining high integration density
2Productivity
If the minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but additional manufacturing challenges and defects arise
Solution Approach 1:
The protective layer is deposited beforehand to simplify subsequent manufacturing steps. By preparing this layer in advance, the patent reduces manufacturing complexity associated with handling miniaturized features, as the protective layer prevents damage during substrate etching and simplifies the overall fabrication process
Solution Approach 2:
The protective layer acts as an intermediary between the source/drain regions and the etching process. This intermediate layer facilitates the manufacturing process by protecting sensitive regions during substrate removal, thereby reducing manufacturing challenges associated with high integration density without compromising ease of manufacture
3Productivity
If source/drain contacts are formed in miniaturized devices, then integration density improves, but contact reliability and manufacturing yield deteriorate
Solution Approach 1:
The protective layer is formed before source/drain contact processing to ensure precise contact formation. This preliminary protective layer prevents damage during substrate etching and subsequent contact formation steps, thereby maintaining manufacturing precision even as device dimensions are reduced for higher integration density
Solution Approach 2:
The protective layer serves as a cushioning layer deposited in advance to protect source/drain regions from damage during manufacturing. This beforehand protection ensures that miniaturized source/drain contacts can be formed with high precision, preventing defects that would otherwise arise from the vulnerability of miniaturized structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing defects and enhances the integration density of transistors by providing reliable source/drain contacts, improving the performance and yield of semiconductor devices.
Implementation Method 1
a majority of the semiconductor substrate is etched away, leaving a portion to cover the edge regions of the source/drain regions
Data Source
AI summary
A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.