Backside Source/Drain Replacement for Semiconductor Devices
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Solution Overview
Problem
In semiconductor device fabrication, the thermal requirements of gate processing are incompatible with high doping levels in source/drain regions, leading to diffusion issues that degrade transistor performance, especially when forming ohmic contacts with high parasitic external resistance.
Innovation Solution
A backside source/drain replacement technique is employed, where a sacrificial material with low or no doping is deposited during front-end processing, and later replaced with high-doping material after bonding the transfer wafer to a host wafer, using a seed layer with a lower etch rate to facilitate the removal of the sacrificial material and regrowth of the final source/drain material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high doping levels are applied in source/drain regions during front-end processing, then ohmic contact properties are improved, but dopant diffusion into the channel region occurs during subsequent gate processing
Solution Approach 1:
The source/drain regions are segmented into two distinct parts: a sacrificial portion formed during front-end processing with low or no doping, and a final portion formed after gate processing with high doping. This segmentation allows each part to serve its specific function without interfering with the other, resolving the contradiction between achieving good ohmic contacts and preventing dopant diffusion.
Solution Approach 2:
The sacrificial source/drain portion is formed in advance during front-end processing before gate processing occurs. This preliminary action prepares the structure for subsequent steps while avoiding the harmful effect of early high doping. The sacrificial material is later removed and replaced with highly doped material after the gate is formed, ensuring no dopant diffusion occurs during gate processing.
2Stability of the object's composition
If low or no doping is used in source/drain regions during front-end processing, then dopant diffusion is prevented, but parasitic external resistance increases
Solution Approach 1:
The sacrificial source/drain portion is formed in advance with low or no doping to maintain compositional stability and prevent dopant diffusion during gate processing. This preliminary low-doping structure serves as a placeholder that protects the channel region. After gate processing is complete, the sacrificial material is removed and replaced with highly doped material to achieve low parasitic resistance, thus resolving the contradiction between preventing diffusion and reducing resistance.
Solution Approach 2:
The doping parameter of the source/drain regions is changed dynamically through the fabrication process. Initially, the sacrificial portion has low or no doping to prevent diffusion. Later, after gate processing, the final portion is formed with high doping to reduce parasitic resistance. This temporal change in doping parameters resolves the contradiction between maintaining compositional stability and achieving low resistance.
3Reliability
If sacrificial source/drain material is removed through backside processing, then interface cleanliness is improved and dopant diffusion is prevented, but additional fabrication steps are required
Solution Approach 1:
The removal of sacrificial source/drain material is performed through the backside of the substrate rather than from the frontside. This inversion of the removal direction allows for cleaner interface preparation and better access to the sacrificial material without interfering with other frontside structures. The backside removal approach, combined with selective etching through opened trenches, achieves superior interface cleanliness while managing the increased process complexity.
4Stability of the object's composition
If final source/drain material is formed after gate processing, then dopant diffusion into channel is prevented, but processing time increases
Solution Approach 1:
The source/drain formation process is segmented into two distinct phases: front-end formation of sacrificial material and back-end formation of final material. This segmentation allows gate processing to occur in between, preventing dopant diffusion. Although this increases total processing time, it ensures compositional stability of the channel region, which is the higher priority for device performance.
Solution Approach 2:
The doping parameter is changed at a specific point in the fabrication timeline - after gate processing is complete. This temporal parameter change ensures that the channel region composition remains stable during gate formation, while still allowing high doping to be applied to the source/drain regions in the final step to achieve low parasitic resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic external resistance and improves ohmic contact properties by maintaining interface cleanliness and preventing dopant diffusion into the channel region, thereby enhancing transistor performance.
Implementation Method 1
The sacrificial S/D material is removed through backside S/D contact trenches to the S/D regions by selective etching using the etch rate difference between the sacrificial S/D material and the channel material
Implementation Method 2
The final S/D material is formed using the seed layer to the S/D contact trenches and backside contact trenches by physical vapor deposition (PVD), chemical vapor deposition (CVD), or other suitable deposition techniques
Implementation Method 3
The final S/D material is formed using the seed layer to the S/D contact trenches and backside contact trenches by physical vapor deposition (PVD), chemical vapor deposition (CVD), or other suitable deposition techniques
Implementation Method 4
The final S/D material may include dopants (e.g., suitable n-type or p-type dopants) in concentrations relatively higher than what would have been practical if the final S/D material was formed during frontside processing of the device layer, such as greater than 1E19 or 1E20, or even 1E21, atoms per cubic cm. In some cases, the S/D material is highly doped to promote ohmic contact
Implementation Method 5
The final S/D material is formed using the seed layer to the S/D contact trenches and backside contact trenches by physical vapor deposition (PVD), chemical vapor deposition (CVD), or other suitable deposition techniques, and may include dopants (e.g., suitable n-type or p-type dopants)
Data Source
AI summary
Techniques are disclosed for backside source/drain (S/D) replacement for semiconductor devices with metallization on both sides (MOBS). The techniques described herein provide methods to recover or otherwise facilitate low contact resistance, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some cases, the techniques include forming sacrificial S/D material and a seed layer during frontside processing of a device layer including one or more transistor devices. The device layer can then be inverted and bonded to a host wafer. A backside reveal of the device layer can then be performed via grinding, etching, and/or CMP processes. The sacrificial S/D material can then be removed through backside S/D contact trenches using the seed layer as an etch stop, followed by the formation of relatively highly doped final S/D material grown from the seed layer, to provide enhanced ohmic contact properties. Other embodiments may be described and/or disclosed.