Backside Source-Drain Interconnects for Crowded Logic Cell Routing
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Solution Overview
Problem
The challenge of reducing the size of memory and logic cells in integrated circuits while efficiently routing logic signals between transistor elements is complicated by crowded metal lines and parasitic effects, leading to inefficient use of space in the interconnect region.
Innovation Solution
Implementing backside interconnect structures that connect transistor source or drain regions, replacing frontside local interconnect layers to free up space for metal 0 signal tracks, using conductive materials like tungsten, titanium, tantalum, ruthenium, molybdenum, or cobalt, and allowing for non-linear shapes to connect misaligned regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If frontside local interconnect layers are used to route logic signals between transistor elements, then signal routing is achieved, but space utilization becomes inefficient and metal lines become crowded
Solution Approach 1:
The patent moves the local interconnect function from the frontside (2D plane) to the backside (third dimension), creating backside contacts that extend through the substrate thickness. This dimensional transition allows interconnect routing to occur in a previously unused spatial zone, freeing up frontside interconnect region space while maintaining signal routing capability.
Solution Approach 2:
Instead of routing interconnect signals from the frontside of the substrate to the frontside (conventional approach), the patent inverts the approach by routing signals from the backside of the substrate to the frontside through backside contacts. This inversion eliminates the need for crowded frontside local interconnect layers.
2Quantity of substance
If device spacing is reduced at the device layer to increase density, then more devices fit in the same area, but routing multiple logic signals becomes more difficult and parasitic effects increase
Solution Approach 1:
By transitioning interconnect routing to the backside dimension, the patent enables shorter and more direct signal paths between closely spaced devices. This reduces the length of metal lines in the crowded frontside interconnect region, thereby reducing parasitic resistance and capacitance effects that would otherwise increase with higher device density.
3Quantity of substance
If device spacing is reduced to increase density, then more devices fit in the same area, but metal lines become more crowded and space utilization decreases
Solution Approach 1:
The patent resolves this contradiction by moving the interconnect routing function to the backside dimension, creating a three-dimensional interconnect architecture. This allows high device density to be achieved on the frontside while the backside provides the interconnect routing space, effectively decoupling device density from interconnect space requirements.
Data Source
Figure 1A
Figure 1B~1C
Figure 2A~2B
AI summary
Techniques are provided herein to form an integrated circuit having a backside interconnect structure coupled between different transistor source or drain regions. The backside interconnect structure may be used to replace frontside local interconnect structures, thus freeing up more space in the frontside interconnect region. A first semiconductor device includes a first semiconductor region extending between a first source or drain region and a second source or drain region, and a second semiconductor device includes a second semiconductor region extending between a third source or drain region and a fourth source or drain region. Each of the source or drain regions have corresponding backside contacts coupled to a bottom surface of the source or drain region. A backside conductive layer may extend beneath the semiconductor devices and be coupled to any of the backside contacts to provide connection between the corresponding source or drain regions.