Backside Source/Drain Via Structure for Scaled FinFET Connectivity
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down integrated circuits (ICs) while maintaining functional density and efficiency, particularly in forming small-sized semiconductor devices with effective source/drain structures.
Innovation Solution
The method involves forming a backside source/drain via under a source/drain structure, which includes creating a multilayer interconnection structure on a carrier substrate, patterning semiconductor fins, and forming source/drain epitaxial structures in recesses within these fins, ensuring electrical connection to the backside source/drain contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but manufacturing precision and electrical performance become more difficult to maintain
Solution Approach 1:
The patent introduces a vertical via structure extending through the semiconductor fin from the front surface to the back surface, utilizing the third dimension (depth/vertical direction) to establish electrical connections. This vertical connection path allows source/drain contacts to be formed on both front and back surfaces, improving electrical performance without increasing lateral footprint, thus enabling continued scaling while maintaining performance requirements
2Area of stationary object
If device size is scaled down, then more devices can be integrated per chip area, but source/drain connectivity and electrical performance deteriorate
Solution Approach 1:
The via structure is nested within the semiconductor fin, with the via extending through the fin thickness and being surrounded by the fin structure. The source/drain contacts on the front and back surfaces are electrically connected through this nested via structure, creating a compact three-dimensional configuration that maintains electrical performance while minimizing lateral space requirements
Solution Approach 2:
By transitioning from planar two-dimensional contacts to a three-dimensional via structure that penetrates the fin thickness, the patent creates additional electrical connection pathways in the vertical dimension. This allows effective source/drain connectivity to be maintained even as the lateral device dimensions are reduced for higher integration density
3Ease of manufacture
If conventional source/drain contact formation is used, then manufacturing process is simpler, but electrical connectivity and device performance are insufficient for scaled devices
Solution Approach 1:
The source/drain contact structure is segmented into multiple components: a front surface contact, a back surface contact, and a via extending between them. This segmentation creates multiple electrical connection points and pathways, improving overall electrical connectivity and reliability. The segmented structure can be formed using modified conventional processes, balancing manufacturing feasibility with performance requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of smaller-sized semiconductor devices with improved electrical performance by enhancing the connectivity and efficiency of the source/drain structures, thus supporting the continued scaling down of ICs.
Implementation Method 1
a semiconductive layer is formed over the first source/drain contact and the first interlayer dielectric layer
Implementation Method 2
a semiconductive layer is formed over the first source/drain contact and the first interlayer dielectric layer
Implementation Method 3
The semiconductor fin is patterned to form a first recess and a second recess in the semiconductor fin, such that the first recess exposes the first source/drain contact
Implementation Method 4
First and second source/drain epitaxial structures are respectively formed in the first and second recesses of the semiconductor fin such that the first source/drain epitaxial structure is electrically connected to the first source/drain contact
Data Source
AI summary
A method includes forming a first multilayer interconnection structure over a carrier substrate. A first interlayer dielectric (ILD) layer is deposited over the first multilayer interconnection structure. A first source/drain contact is formed in the first ILD layer. After forming the first source/drain contact, a semiconductive layer is formed over the first source/drain contact and the first ILD layer. The semiconductive layer is patterned to form a semiconductor fin over the first source/drain contact. A gate structure is formed across the semiconductor fin. The semiconductor fin is patterned to form a first recess and a second recess in the semiconductor fin, such that the first recess exposes the first source/drain contact. First and second source/drain epitaxial structures are respectively formed in the first and second recesses of the semiconductor fin such that the first source/drain epitaxial structure is electrically connected to the first source/drain contact.