Backside Source/Drain Via Layout for Scaled Semiconductor Fins
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down device sizes while maintaining efficient production and reducing costs, particularly in forming small-sized semiconductor devices with effective backside source/drain structures that enhance electrical performance.
Innovation Solution
The method involves forming a backside source/drain via under a source/drain structure, using a combination of photolithography and self-aligned processes for patterning fins, and integrating a multilayer interconnection structure with tapered conductive vias and metal lines to improve device architecture and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device geometry size is decreased to increase functional density, then production efficiency and cost are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent introduces a backside source/drain via structure that extends vertically through the substrate, adding a vertical dimension to the source/drain connection. This allows electrical connectivity to be established from the backside of the device, effectively utilizing the third dimension (depth/vertical direction) to reduce lateral footprint and enable higher functional density without proportionally increasing manufacturing complexity
2Productivity
If device geometry size is decreased to increase functional density, then production efficiency and cost are improved, but manufacturing precision requirements increase
Solution Approach 1:
The backside source/drain via structure is formed through preliminary substrate thinning and via creation steps performed before final device assembly. By preparing the vertical connection pathways in advance through the substrate, the patent enables subsequent alignment and connection processes to be performed with relaxed precision requirements, as the critical dimensional tolerances are established during the preliminary via formation stage rather than during final assembly
3Reliability
If source/drain contact size is enlarged to improve electrical performance, then electrical conductivity is improved, but device area increases
Solution Approach 1:
The patent transitions the source/drain contact from a purely lateral planar structure to a three-dimensional structure that extends vertically through the substrate via backside vias. This vertical extension provides additional electrical conduction pathways in the depth direction, effectively increasing the total contact area and electrical performance without proportionally increasing the lateral footprint, thus maintaining compact device area
Data Source
AI summary
A method includes forming a first multilayer interconnection structure over a carrier substrate. A first interlayer dielectric (ILD) layer is deposited over the first multilayer interconnection structure. A first source/drain contact is formed in the first ILD layer. After forming the first source/drain contact, a semiconductive layer is formed over the first source/drain contact and the first ILD layer. The semiconductive layer is patterned to form a semiconductor fin over the first source/drain contact. A gate structure is formed across the semiconductor fin. The semiconductor fin is patterned to form a first recess and a second recess in the semiconductor fin, such that the first recess exposes the first source/drain contact. First and second source/drain epitaxial structures are respectively formed in the first and second recesses of the semiconductor fin such that the first source/drain epitaxial structure is electrically connected to the first source/drain contact.