3D Memory Backside Source Mesh for Dense Low-Capacitance Routing
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Solution Overview
Problem
Planar memory cell technologies face challenges in scaling due to cost and complexity issues as feature sizes approach their limits, leading to density limitations in memory devices.
Innovation Solution
The development of three-dimensional (3D) memory devices with backside source contact interconnect structures, which allows for more efficient use of backside area and optimized metal routing, thereby improving electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cell scaling is continued to increase density, then memory density improves, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) stacked architecture. Multiple memory stacks are formed vertically on the substrate, with bit lines extending through multiple stacks and source lines positioned at different heights. This vertical stacking enables significantly higher memory density without proportionally increasing manufacturing complexity, as the basic memory cell structure remains similar across stacks.
2Quantity of substance
If feature sizes are reduced to increase memory density, then memory density improves, but process fabrication becomes more challenging and costly
Solution Approach 1:
The memory device is divided into multiple discrete memory stacks formed in parallel on the substrate. Each stack contains a complete set of memory cells with channel structures, gate lines, and source/drain regions. This segmentation allows standard fabrication processes to be applied repeatedly to create multiple independent stacks, avoiding the need to scale down individual feature sizes while still achieving high overall density through vertical integration.
3Device complexity
If conventional interconnect structures are used in 3D memory, then routing is simpler, but electrical performance suffers due to increased leakage current and parasitic capacitance
Solution Approach 1:
Source lines are positioned at different vertical heights corresponding to different memory stacks, with source contacts extending vertically through the substrate to connect to source lines at appropriate levels. This three-dimensional interconnect arrangement reduces parasitic capacitance between adjacent conductors by increasing their vertical separation, while still providing efficient routing to all memory stacks through the vertical dimension.
Data Source
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AI summary
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, a plurality of channel structures each extending vertically through the memory stack, a semiconductor layer above and in contact with the plurality of channel structures, a plurality of source contacts above the memory stack and in contact with the semiconductor layer, a plurality of contacts through the semiconductor layer, and a backside interconnect layer above the semiconductor layer including a source line mesh in a plan view. The plurality of source contacts are distributed below and in contact with the source line mesh. A first set of the plurality of contacts are distributed below and in contact with the source line mesh.