Backside Source Power Supply Mesh for 3D Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current three-dimensional memory devices with vertical NAND strings face challenges in efficiently supporting write, read, and erase operations due to limitations in the support circuitry, particularly in providing effective power supply mechanisms for the memory cells.
Innovation Solution
A semiconductor structure is developed with a memory die bonded to a logic die, featuring a backside source power supply mesh. This structure includes an alternating stack of insulating and conductive layers, memory openings filled with vertical semiconductor channels and memory films, and a source power supply mesh electrically connected to the source layer through conductive material portions extending through a backside isolation dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional support circuitry is used for three-dimensional memory devices, then device complexity is reduced, but power supply efficiency for memory cells deteriorates
Solution Approach 1:
The patent introduces a backside power supply mesh located on the rear surface of the memory device, transitioning the power delivery system from a planar top-side configuration to a three-dimensional structure that utilizes the backside surface. This dimensional change enables direct vertical power delivery to the source layer through the substrate, significantly improving power supply efficiency without adding lateral complexity to the existing circuitry layout.
Solution Approach 2:
The patent employs an intermediary power distribution network consisting of a backside mesh structure with multiple contact points that couples the power supply to the source layer. This intermediary mesh acts as a mediator between the external power source and the vertical NAND strings, distributing power uniformly across multiple locations and improving overall power delivery efficiency while maintaining compatibility with existing device architecture.
2Quantity of substance
If vertical NAND strings are implemented for high density, then storage capacity increases, but operational performance deteriorates
Solution Approach 1:
The patent segments the power supply interface into multiple discrete contact points distributed across the backside surface, with each contact point serving specific vertical NAND string regions. This segmentation allows independent optimization of power delivery to different memory regions, improving operational performance while maintaining the high storage capacity enabled by vertical NAND architecture.
Solution Approach 2:
By moving the power supply interface to the backside dimension, the patent enables direct vertical power delivery paths that align with the vertical NAND string orientation. This dimensional alignment reduces current path length and resistance, improving write, read, and erase operation speeds without compromising the high density achieved through vertical stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the operational efficiency of three-dimensional memory devices by providing a robust power supply mechanism, improving the performance of write, read, and erase operations in vertical NAND strings, thereby addressing the limitations of existing technologies.
Implementation Method 1
a source power supply mesh comprising a planar portion of a source-side electrically conductive layer that is located over a backside of the backside isolation dielectric layer and electrically connected to the source layer by conductive material portions that extend through the backside isolation dielectric layer
Data Source
AI summary
A semiconductor structure includes a memory die bonded to a logic die. The memory die includes an alternating stack of insulating layers and electrically conductive layers; memory openings extending through the alternating stack, memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film, a source layer contacting the vertical semiconductor channels, a backside isolation dielectric layer contacting a backside surface of the source layer, and a source power supply mesh including a planar portion of a source-side electrically conductive layer that is located on a backside of the backside isolation dielectric layer and electrically connected to the source layer by conductive material portions that extend through the backside isolation dielectric layer.