Backside Source/Drain Contact Layout for Wider Power Rails
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor device size shrinks, there is a challenge in forming metal power rails and signal lines due to reduced space, and forming a silicide layer between an active semiconductor region and a backside metal contact is particularly difficult.
Innovation Solution
The solution involves forming metal contacts on the backside of the substrate after completing BEOL processes, allowing for enlarged gate widths in field-effect transistors and increased power rail widths, using backside processes that maintain BEOL integrity, and creating a conductive feature that connects with the source/drain feature through a silicide layer formed on the front side.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If metal power rails and signal lines are formed on the front side of the substrate, then electrical connections are established, but the gate width is reduced and routing complexity increases
Solution Approach 1:
The patent moves the power rail formation from the front side (2D plane) to the back side of the substrate, utilizing the third dimension (depth/thickness) to resolve the conflict between routing complexity and gate width. By forming power rails on the back side, the front side gate area is preserved while power distribution is achieved through the substrate thickness dimension.
2Reliability
If a silicide layer is formed between the active semiconductor region and backside metal contact, then electrical connection is improved, but the fabrication process becomes more difficult
Solution Approach 1:
The silicide layer is formed on the active semiconductor region before the backside metal contact is created. This preliminary formation of the silicide layer simplifies the overall fabrication process by preparing the electrical connection interface in advance, making the subsequent backside contact formation more straightforward and reliable.
Data Source
AI summary
The present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.