Backside Spacer Layout for Lower-Resistance Power Rail Contacts
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Solution Overview
Problem
Existing three-dimensional multi-gate devices face challenges with routing resistance, alignment margins, and layout flexibility due to conventional backside power rails, which affect the performance and reliability of semiconductor devices.
Innovation Solution
The use of a thicker backside spacer instead of a dielectric protection layer to prevent backside leakage, allowing for larger backside via and silicide layer sizes, thereby improving power rail alignment and reducing routing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dielectric protection layer is used to prevent backside leakage, then reliability is improved, but device complexity and routing resistance increase
Solution Approach 1:
The patent removes the dielectric protection layer from the backside structure and replaces it with a spacer formed by selective etching. This extraction of the unnecessary dielectric layer simplifies the overall device structure while maintaining the essential function of preventing backside leakage through the spacer structure that defines the via opening boundaries.
Solution Approach 2:
Instead of using a dielectric material to prevent leakage (conventional approach), the patent inverts the approach by using a spacer structure formed through selective etching of sacrificial material. The spacer is created by removing material rather than adding protective material, fundamentally changing the methodology from protection-by-addition to protection-by-precise-formation.
2Ease of manufacture
If conventional backside power rails are used, then manufacturing is simplified, but routing resistance and alignment margins deteriorate
Solution Approach 1:
The patent changes the dimensional parameters of the backside via by enabling larger via sizes through the spacer structure. The spacer thickness directly controls the via opening size, allowing optimization of via dimensions to reduce routing resistance while maintaining alignment margins. This parameter control through spacer thickness provides flexibility in optimizing electrical performance.
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.