Backside Spacer Layout for Low-Resistance Power Rail Vias
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Solution Overview
Problem
Conventional three-dimensional multi-gate devices face challenges with backside power rails due to routing resistance, alignment margins, and layout flexibility, exacerbated by dielectric protection layers that cause high parasitic resistance and small metal fill windows.
Innovation Solution
Employing a backside spacer instead of a dielectric protection layer to enhance isolation and enlarge the backside via size, reducing routing resistance and mitigating overlay shifting issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dielectric protection layer is used to protect the backside via, then the via is protected from damage, but the parasitic resistance increases and the metal fill window decreases
Solution Approach 1:
The patent removes the dielectric protection layer from the backside via structure. Instead of protecting the via with a dielectric layer that causes high parasitic resistance, the invention uses a different approach where the via is protected through the etch selectivity between the bottom semiconductor layer and the backside dielectric layer, eliminating the need for an additional protection layer and thereby reducing parasitic resistance.
Solution Approach 2:
The patent introduces a bottom semiconductor layer as an intermediary structure between the substrate and the backside dielectric layer. This bottom semiconductor layer serves as both a structural component and a protective element during etching processes, replacing the traditional dielectric protection layer and enabling lower parasitic resistance while maintaining via integrity.
2Reliability
If a dielectric protection layer is formed along the sidewalls of the backside via, then the via is isolated, but the metal fill window becomes small and routing resistance increases
Solution Approach 1:
The patent eliminates the dielectric protection layer that was previously formed along the sidewalls of the backside via. By removing this layer, the metal fill window is enlarged, allowing for better metal filling and reduced routing resistance while maintaining adequate isolation through the bottom semiconductor layer and etch selectivity mechanisms.
3Ease of manufacture
If the bottom semiconductor layer is removed completely, then the backside via can be formed directly, but the isolation between the via and the semiconductor structure is compromised
Solution Approach 1:
The patent maintains the bottom semiconductor layer in specific regions to provide local isolation functionality. Rather than completely removing the bottom semiconductor layer, the invention preserves it in areas where isolation is needed while allowing via formation in regions where the layer provides appropriate etch selectivity and protection, achieving both ease of manufacture and reliable isolation.
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.