Backside Integrated Spiral Inductor Fabrication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for fabricating integrated spiral inductors face challenges in achieving high Q-factor, high self-resonance frequency, and reduced silicon area consumption while minimizing substrate loss, often resulting in reliability issues and increased complexity.
Innovation Solution
The method involves performing a standard front-side CMOS manufacturing process, permanently bonding a high-resistivity carrier wafer to the semiconductor wafer, thinning the silicon substrate, removing the semiconductor substrate under the inductor area, and filling the gap with dielectric material, followed by forming the spiral inductor on the backside and connecting it to CMOS circuits through through-silicon vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a solid ground shield is inserted between the inductor coil and silicon substrate, then substrate loss is reduced, but eddy currents are generated in the shield lowering the Q-factor
Solution Approach 1:
The patent extracts the problematic silicon substrate material from the region underneath the inductor coil by etching a trench and removing the substrate, thereby eliminating the source of substrate loss without introducing a ground shield that would generate eddy currents
Solution Approach 2:
The patent introduces a dielectric material as an intermediary substance to fill the etched trench, providing electrical isolation and maintaining mechanical support while preventing direct contact between the inductor coil and conductive substrate that would cause loss
2Reliability
If a patterned ground shield is used to suppress eddy currents, then Q-factor is improved, but additional parasitic capacitance is generated lowering the SRF
Solution Approach 1:
The patent removes the ground shield structure entirely and instead extracts the conductive substrate material from underneath the inductor, eliminating both the eddy current problem and the parasitic capacitance issue simultaneously
3Speed
If a thick dielectric layer is inserted between the inductor and substrate, then parasitic capacitance is reduced, but additional process steps are required increasing manufacturing complexity
Solution Approach 1:
The patent merges the trench etching step with the standard CMOS fabrication process flow, performing the substrate removal and dielectric filling during normal manufacturing operations rather than requiring separate additional process steps
4Loss of energy
If the inductor is placed on a thick polyimide layer, then substrate loss is reduced, but the method requires additional process steps not part of standard CMOS fabrication
Solution Approach 1:
The patent changes the physical and electrical parameters of the substrate region underneath the inductor by removing the conductive silicon material and replacing it with a non-conductive dielectric material, thereby reducing substrate loss while maintaining compatibility with standard CMOS fabrication processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces substrate loss, enhances Q-factor and self-resonance frequency, and minimizes silicon area consumption, while simplifying the inductor's design and reducing noise coupling, thereby improving the performance and reliability of the integrated spiral inductor.
Implementation Method 1
permanently bonding a high-resistivity carrier wafer to the semiconductor wafer
Implementation Method 2
filling the gap with dielectric material
Implementation Method 3
connecting it to CMOS circuits through through-silicon vias
Data Source
Figure 1
Figure 2
Figure 3
AI summary
After finishing of the front side CMOS manufacturing process, the silicon wafer is permanently bonded with its front side onto a carrier wafer. The carrier wafer is a high resistivity silicon wafer or a wafer of a dielectric or of a ceramic material. The silicon substrate of the device wafer is thinned from the back side such that the remaining silicon0thickness is only a few micrometers. In the area dedicated to a spiral inductor, the substrate material is entirely removed by a masked etching process and the resulting gap is filled with a dielectric material. A spiral inductor coil is formed on the backside of the wafer on top of the dielectric material. The inductor coil is connected to the CMOS circuits on the front side by through-silicon vias.