Backside-to-Backside Stacked Die Package with Vertical Interconnects
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Solution Overview
Problem
Conventional stacked die structures face issues with long metal trace paths, thermal stresses, and excessive assembly height due to system architecture, which affect communication efficiency and thermal stability.
Innovation Solution
The solution involves stacking semiconductor die structures backside-to-backside with surface-activated bonding (SAB) or solder bump bonding, using underfill materials and molding compounds to create a compact assembly that reduces thermal stresses and enhances vertical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional stacked die structures are used with traditional interconnection methods, then the assembly height increases excessively, but the signal path length becomes unacceptably long
Solution Approach 1:
The patent transitions from planar interconnection to vertical three-dimensional interconnection by stacking die structures vertically. This dimensional change allows signals to travel directly between stacked dies through vertical vias and interconnect structures, dramatically reducing signal path length while maintaining compact assembly height through the vertical stacking architecture.
2Power
If the lower die carries the entire power source for upper dies, then power delivery is achieved, but thermal stresses become undesirable
Solution Approach 1:
The patent segments the power delivery function by distributing power sources across multiple die structures rather than concentrating them in the lower die. Each die can have its own power source or share power sources equidistantly, dividing the thermal load and preventing excessive thermal stress accumulation in any single die.
Solution Approach 2:
The patent moves power sources from a single-location (lower die only) arrangement to a distributed three-dimensional arrangement where power sources are located at multiple vertical levels. This spatial redistribution balances thermal generation across the stacked structure, reducing thermal stress while maintaining adequate power delivery to all dies.
3Productivity
If metal traces travel long paths to reach active regions, then system architecture requirements are met, but communication efficiency decreases
Solution Approach 1:
The patent implements vertical interconnection through stacked dies with direct vias and interconnect structures between active regions of adjacent dies. This vertical pathway in the third dimension replaces long planar metal traces, dramatically reducing signal path length and improving communication efficiency between functional blocks distributed across multiple dies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables shorter signal paths, efficient communication, and reduced thermal stresses, allowing for compact and efficient integration of multiple die structures while minimizing thermal expansion mismatch.
Implementation Method 1
stacked with the backside metallization surface of the second die structure positioned on the backside metallization surface of the first die structure
Implementation Method 2
solder bump bonding
Implementation Method 3
reduced thermal stresses... minimizing thermal expansion mismatch
Data Source
AI summary
The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a plurality of vias, the vias forming electrical connections between the active region and the backside metal regions. The first and second semiconductor die structures are stacked together with at least one of the metal regions on the backside of the first semiconductor die structure in direct contact with at least one of the metal regions on the back side of the second semiconductor die structure. Other embodiments are described and claimed.