Backside Staircase Contacts for Lower-Cost 3D Memory Stacks
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Solution Overview
Problem
The existing manufacturing processes for memory devices with three-dimensionally stacked memory cells face high costs due to the complexity of etching processing and the need for multiple steps, which increases the chip area and manufacturing expenses.
Innovation Solution
A bonded structure memory device is developed, where contacts for stacked wiring lines penetrate from the backside of a staircase structure, and replacement processing forms stacked wiring lines after bonding, integrating slit and contact hole formation using a stopper layer, reducing the number of high-aspect-ratio etching steps and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional etching processing is used for three-dimensionally stacked memory cells, then memory storage capacity is achieved, but manufacturing cost increases due to process complexity and multiple steps
Solution Approach 1:
The patent applies preliminary action by forming a stopper layer and defining terrace portions before the bonding process. The stopper layer is prepared in advance on one substrate, and the staircase structure with exposed terrace portions is created beforehand on the other substrate. This preliminary preparation enables subsequent simplified processing after bonding, reducing the overall manufacturing complexity while maintaining high storage capacity through three-dimensional stacking.
2Manufacturing precision
If multiple etching steps are used to form contacts and slits, then precise contact formation is achieved, but chip area increases and manufacturing expense rises
Solution Approach 1:
The patent merges the formation of contacts and slits into a single integrated process. After bonding the two substrates, both the contact holes (penetrating through the first substrate to reach terrace portions) and the slits (formed in the second substrate) are created simultaneously using one etching step. This merging eliminates the need for separate processing steps, reduces chip area, and lowers manufacturing expenses while maintaining precise contact formation through the pre-defined terrace portions.
3Reliability
If high-aspect-ratio etching is performed multiple times, then stacked wiring line connectivity is achieved, but manufacturing cost increases
Solution Approach 1:
The patent applies preliminary action by pre-forming the staircase structure with exposed terrace portions before bonding. This preliminary structure serves as a template that guides subsequent contact hole formation, ensuring proper connectivity to stacked wiring lines without requiring multiple high-aspect-ratio etching steps. The terrace portions act as natural etching stops and alignment references, reducing manufacturing complexity and cost while maintaining reliable wiring line connectivity.
Data Source
AI summary
A memory device according to an embodiment includes a substrate, first conductive layers, an insulating layer, pillars, and contacts. The first conductive layers are provided above the substrate. The insulating layer is provided above the first conductive layers. The pillars have portions facing the first conductive layers functioning as memory cells. The contacts are connected to the first conductive layers, respectively. Each of the first conductive layers has, between itself and the substrate, a terrace portion not overlapping with another first conductive layer. Each of the contacts penetrates the insulating layer and is, in a bottom portion thereof, connected to the terrace portion of one first conductive layer among the first conductive layers.