Backside STI Substrate Cut for Latch-Up-Resistant Logic
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Solution Overview
Problem
The miniaturization of transistors in semiconductor devices leads to increased density and susceptibility to latch-up, a condition where parasitic structures form low-impedance paths causing short circuits, particularly at high operating frequencies, leading to potential device failure.
Innovation Solution
A semiconductor device design with a backside substrate cut under shallow trench isolation (STI) structure, incorporating a backside power delivery network (BSPDN) and dielectric layers to isolate and electrically connect different substrate portions, preventing direct contact and minimizing latch-up risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor miniaturization is pursued to increase density, then computational power and energy efficiency are improved, but susceptibility to latch-up increases
Solution Approach 1:
The substrate is segmented into isolated regions using shallow trench isolation (STI) structures that extend vertically between source/drain regions. This segmentation breaks potential parasitic current paths, preventing latch-up while maintaining high transistor density for improved computational power.
Solution Approach 2:
The isolation structure extends vertically into the substrate, adding a vertical dimension to the isolation approach. This vertical STI structure creates multiple isolation barriers that effectively block parasitic paths without reducing horizontal transistor density, thus maintaining productivity while improving reliability.
2Reliability
If vertical substrate portions are isolated by STI structure, then latch-up risk is reduced, but device structure complexity increases
Solution Approach 1:
The shallow trench isolation structure performs multiple functions simultaneously: it provides electrical isolation between vertical substrate portions, defines transistor regions, and serves as a mechanical support structure. This merging of functions reduces overall device complexity while maintaining effective latch-up prevention.
Solution Approach 2:
The STI structure is designed to serve multiple purposes: electrical isolation, mechanical support, and process alignment reference. This multi-functionality reduces the need for additional separate structures, thereby reducing overall device complexity while achieving reliable latch-up prevention.
Data Source
AI summary
A semiconductor device includes a logic device including a first portion of a first substrate extending vertically below a first source/drain region, a second portion of the first substrate extending vertically below a second source/drain region, a first shallow trench isolation (STI) extending vertically and isolating the first portion of the first substrate and the second portion of the first substrate, a backside power delivery network (BSPDN) below the logic device, a first dielectric layer extending vertically through the horizontal portion of the first substrate and connected to the first STI and the BSPDN, and an oxide trench wall over sidewalls of a backside contact.


