Backside Stress Layer for Semiconductor Channel Strain
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for applying stress layers to semiconductor structures often compromise their integrity due to early formation and subsequent thermal processing, leading to reduced effectiveness, and these stress layers are frequently removed during packaging, thereby not benefiting the final structure's performance.
Innovation Solution
A method for fabricating semiconductor structures with backside stress layers formed after device fabrication and thermal processing, using dielectric layers with conductive connections, and applying uniaxial compressive or tensile stress to channel regions, which are not removed before packaging, allowing for enhanced strain and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the stress layer is formed on the backside of the FET structure early in the FET structure fabrication, then the stress layer can be applied to the channel region, but the stress layer is removed when the structure is thinned for packaging and assembly, thus the final structure cannot benefit from the presence of the stress layer
Solution Approach 1:
The stress layer is formed on the backside of the semiconductor substrate after the FET structure is completely fabricated and before packaging, ensuring the stress layer is already in place and protected when the substrate is thinned for packaging. This preliminary action prevents the stress layer from being removed during subsequent packaging processes.
2Reliability
If the stress layer is formed on the backside of the transistors early in fabrication, then the stress layer can be applied, but the stress layer is subjected to subsequent thermal processing which jeopardizes the integrity of the stress layer
Solution Approach 1:
The stress layer is formed after all thermal processing steps are completed during FET fabrication, eliminating exposure to subsequent thermal processing that would compromise the stress layer integrity. The stress layer is applied in a final step before packaging, ensuring it remains intact throughout the manufacturing process.
3Reliability
If conductive contacts are formed through a stress layer applied to the top or front side of the transistors, then electrical connections can be established, but the interruption of the stress layer by a conductive contact compromises the integrity of the stress layer, thus decreasing the stress it applies to the channel regions
Solution Approach 1:
The stress layer is moved from the front side (top surface) of the transistor to the backside (opposite surface) of the semiconductor substrate. This dimensional relocation allows conductive contacts to be formed on the front side without interrupting the stress layer, as the stress layer now resides on the opposite surface where it cannot be breached by front-side contacts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures the integrity and effectiveness of the stress layers, providing additional strain to channel regions and improving device performance without being compromised by thermal processes or packaging, and allows for customizable thickness and material selection for the stress layers.
Implementation Method 1
A backside stress layer is formed on a back surface of the semiconductor substrate. The backside stress layer is configured to apply to the channel region of the semiconductor device a uniaxial compressive or tensile stress
Implementation Method 2
The backside stress layer is configured to apply to the channel region of the semiconductor device a uniaxial compressive or tensile stress that, with stresses applied by the plurality of dielectric layers, results in an overall stress exerted on the channel region to achieve a predetermined overall strain of the channel region
Data Source
AI summary
Methods for fabricating semiconductor structures with backside stress layers are provided. In one exemplary embodiment, the method comprises the steps of providing a semiconductor device formed on and within a front surface of a semiconductor substrate. The semiconductor device comprises a channel region. A plurality of dielectric layers is formed overlying the semiconductor device. The plurality of dielectric layers comprises conductive connections that are in electrical communication with the semiconductor device. A backside stress layer is formed on a back surface of the semiconductor substrate. The backside stress layer is configured to apply to the channel region of the semiconductor device a uniaxial compressive or tensile stress that, with stresses applied by the plurality of dielectric layers, results in an overall stress exerted on the channel region to achieve a predetermined overall strain of the channel region.