Backside Super Via Wiring for Lower Voltage Drop in Semiconductors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in achieving improved Power, Performance, and Area (PPA) characteristics, particularly in high-integration and high-reliability applications.
Innovation Solution
The semiconductor device incorporates a substrate with both frontside and backside wiring structures, featuring a super via pattern that intersects and extends through multiple layers of backside wiring patterns, enhancing electrical connectivity and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional wiring structures are used, then manufacturing is simpler, but voltage drop increases and power delivery is insufficient
Solution Approach 1:
The patent introduces a backside wiring structure that utilizes the third dimension (vertical depth) by creating wiring layers on the opposite side of the substrate from the conventional frontside wiring. This dimensional transition allows power delivery networks to route signals through the substrate thickness, effectively adding a new spatial dimension for current flow paths and reducing voltage drop without merely increasing lateral complexity.
Solution Approach 2:
The wiring structure is segmented into distinct frontside and backside components, with the backside wiring structure including separate interlayer insulating films, wiring patterns, and via patterns. This segmentation allows independent optimization of power delivery pathways, enabling targeted reduction of voltage drop in critical regions without requiring complete redesign of the entire wiring system.
2Productivity
If wiring structures are simplified, then manufacturing is easier, but integration level decreases
Solution Approach 1:
The backside wiring structure is formed through preliminary actions including depositing multiple interlayer insulating films, creating via patterns through etching, and forming wiring patterns through sequential deposition and etching processes. These preliminary structuring actions establish a ready-to-use backside wiring network that enables high integration without requiring complex real-time manufacturing adjustments.
Solution Approach 2:
The backside wiring structure employs a nested arrangement where multiple interlayer insulating films are sequentially deposited, with each layer containing wiring patterns and via patterns embedded within. This nested doll-like structure allows multiple wiring layers to be compactly integrated, achieving high integration density while maintaining manufacturability through standardized deposition and etching processes.
3Reliability
If conventional via structures are used, then manufacturing is simpler, but electrical connectivity is insufficient
Solution Approach 1:
Super via patterns are formed to extend through the substrate thickness in the vertical dimension, connecting frontside and backside wiring structures. This dimensional transition creates low-resistance current paths that traverse the substrate depth, significantly improving electrical connectivity and reliability compared to conventional planar via structures that only connect adjacent wiring layers.
Solution Approach 2:
The via structures exhibit local quality differentiation where super via patterns with enhanced dimensions and materials are strategically positioned at critical connection points between frontside and backside wiring, while other via patterns maintain standard specifications. This localized enhancement improves electrical connectivity where needed without uniformly increasing device complexity across the entire structure.
Data Source
AI summary
A semiconductor device comprises a substrate that including a frontside comprising an active region and a backside opposite to the frontside, an electronic element on the active region, a frontside wiring structure electrically connected to the electronic element on the frontside of the substrate, and a backside wiring structure electrically connected to the electronic element on the backside of the substrate. The backside wiring structure includes a plurality of backside wiring patterns sequentially stacked on the backside of the substrate, and a super via pattern that intersects and extends through at least one layer of the plurality of backside wiring patterns.