Backside Through-Wafer Via Fabrication for Low-Impedance Grounding
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Solution Overview
Problem
Semiconductor devices require effective conductive structures that provide reduced impedance ground paths and efficient thermal conduits to manage increasing frequency, speed, and power consumption, while existing methods fall short in achieving these requirements.
Innovation Solution
A method for fabricating a backside through-wafer via in a processed wafer, involving steps such as thinning the substrate, forming a through-wafer via opening, depositing an adhesion/barrier layer, and electrochemically plating metal to create a conductive structure that extends through the wafer, providing both low impedance and thermal conduit functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional conductive structures are used in semiconductor devices, then the devices can operate at lower frequencies and power levels, but the impedance is higher and thermal management is less efficient
Solution Approach 1:
The patent inverts the conventional approach by forming the through-wafer via from the backside of the substrate rather than the frontside. This allows the via to be created after the semiconductor devices are fabricated on the frontside, avoiding disruption to the device structures while still achieving low-impedance ground paths and efficient thermal conduction through the substrate.
Solution Approach 2:
The conductive structure is segmented into multiple components: a through-wafer via extending through the substrate, a via fill material providing low-impedance conduction, and an optional cap structure. This segmentation allows each component to be optimized independently for its specific function while working together to solve the overall problem of high impedance and poor thermal management.
2Manufacturing precision
If through-wafer vias are formed from the frontside, then alignment with device structures can be achieved, but the device structures are damaged or disrupted
Solution Approach 1:
The patent reverses the formation sequence by creating the through-wafer via from the backside of the substrate after the semiconductor devices are fully fabricated on the frontside. This inversion eliminates the risk of damaging device structures during via formation while still achieving precise alignment through backside processing techniques and subsequent cap structure formation.
3Strength
If the substrate is not thinned, then the mechanical strength is maintained, but the via opening formation and metal plating are more difficult
Solution Approach 1:
The patent performs preliminary substrate thinning from the backside before forming the through-wafer via opening. This preliminary action reduces the substrate thickness to make subsequent via formation and metal plating easier while maintaining sufficient mechanical strength through controlled thinning processes and subsequent structural support from the via fill material and cap structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively creates a conductive structure that acts as a low-impedance ground conduit and efficient thermal conduit for semiconductor devices, enhancing their performance and heat management.
Implementation Method 1
depositing an adhesion/barrier layer on the inner wall of the through-wafer via opening
Implementation Method 2
electrochemically plating metal to create a conductive structure that extends through the wafer
Data Source
AI summary
According to an exemplary embodiment, a method for fabricating a backside through-wafer via in a processed wafer includes forming a through-wafer via opening through a substrate and extending the through-wafer via opening through at least one interlayer dielectric layer situated over the substrate. The method further includes forming a metal layer in the through-wafer via opening, where the metal layer forms an electrical connection to substrate. The metal layer is also in electrical contact with an interconnect metal segment situated above the at least one interlayer dielectric layer. The method further includes performing a thinning process to reduce the substrate to a target thickness before forming the through-wafer via opening. The method further includes forming an electrically conductive passivation layer on the metal layer and over a bottom surface of the substrate, where the electrically conductive passivation layer is in electrical contact with the metal layer and the substrate.