Backside Transistor Structure With Dielectric Isolation for Higher Density
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Solution Overview
Problem
Current semiconductor technologies face challenges in miniaturizing structural features to achieve increased performance at lower power levels and costs, as they approach atomic level scaling of micro-devices like logic gates and transistors, requiring innovative approaches to integrate more transistors within a given chip size.
Innovation Solution
The formation of semiconductor structures with back side transistor devices, utilizing a dielectric isolation layer to separate transistors on opposite sides of the structure, allowing for independent source/drain regions and channel layers, enabling the integration of single-crystal channel transistors and back side power distribution networks, which facilitates co-integration with front side transistors and enhances performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional miniaturization techniques are used to increase transistor density, then more transistors can be integrated, but the transistor size approaches atomic limits and manufacturing precision becomes difficult to maintain
Solution Approach 1:
The patent transitions from planar 2D transistors to three-dimensional vertically-stacked transistors, where multiple transistor channels are stacked vertically above a common base. This dimensional change allows increased transistor density without further reducing lateral feature sizes, thereby maintaining manufacturing precision while achieving higher integration density.
Solution Approach 2:
The patent implements nested structures where multiple channel layers are stacked vertically within a compact footprint, and source/drain regions are nested around the channel stack. This nesting approach maximizes the use of vertical space to increase transistor density without proportionally increasing the lateral area, avoiding atomic-level scaling challenges.
2Quantity of substance
If transistor size is reduced to increase integration density, then more transistors fit on chip, but power consumption per transistor increases and performance decreases
Solution Approach 1:
The patent changes the geometric parameters of transistors from lateral scaling to vertical stacking, increasing the effective channel area without reducing the lateral dimensions. This parameter change allows more transistors to be integrated while maintaining adequate channel dimensions for acceptable power consumption and performance characteristics.
Solution Approach 2:
By utilizing the vertical dimension for stacking multiple transistor channels, the patent achieves higher integration density without further lateral miniaturization. This preserves the channel cross-sectional dimensions needed for optimal carrier transport and power efficiency.
3Reliability
If independent source/drain regions are formed for back side transistors, then transistor performance is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the dielectric isolation layer and defining the back side transistor regions before completing the front side transistor fabrication. This preliminary structuring enables subsequent independent source/drain formation on the back side without requiring complete process rework, managing complexity through staged fabrication.
Solution Approach 2:
The patent segments the semiconductor structure into distinct front side and back side transistor regions separated by a dielectric isolation layer. This segmentation allows independent optimization and fabrication of each transistor set, with independent source/drain regions formed on the back side, improving performance while organizing the manufacturing process into manageable segments.
4Area of stationary object
If back side transistor devices are integrated, then chip area utilization is improved, but device complexity and isolation requirements increase
Solution Approach 1:
The patent utilizes the vertical dimension by stacking transistors and forming back side devices on the opposite face of the substrate. This three-dimensional approach doubles the effective chip area utilization without requiring lateral expansion, while the dielectric isolation layer provides the necessary separation to manage device complexity.
Solution Approach 2:
The patent introduces a dielectric isolation layer as an intermediary structure between front side and back side transistors. This intermediate layer provides electrical isolation and mechanical separation, enabling independent operation of back side devices while managing the complexity of having transistors on both sides of the chip.
Data Source
AI summary
A semiconductor structure comprises one or more transistor devices on a first side of the semiconductor structure, one or more transistor devices on a second side of the semiconductor structure, the second side being opposite the first side, and a dielectric isolation layer separating the one or more transistor devices on the first side of the semiconductor structure from the one or more transistor devices on the second side of the semiconductor structure. The one or more transistor devices on the second side of the semiconductor structure comprise channel layers on one side of the dielectric isolation layer and source/drain regions that are independent of source/drain regions of the one or more transistor devices on the first side of the semiconductor structure.