Backside Trench Capacitors for High-Density IC Capacitance
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Solution Overview
Problem
Traditional metal-insulator-metal (MIM) or metal-oxide-metal (MOM) capacitors require large areas on integrated circuits (ICs) for high capacitance values, increasing costs and limiting mobile device size and functionality.
Innovation Solution
The formation of backside trench capacitors on semiconductor substrates, where trenches are lined with conductive and dielectric layers to create capacitors, allowing for high capacitance density in a smaller footprint and enabling the stacking of substrates to form three-dimensional ICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional MIM or MOM capacitors are used to achieve high capacitance values, then capacitance is improved, but area occupied on the IC increases
Solution Approach 1:
The patent moves capacitor formation from the traditional planar surface of the IC to the backside of the substrate, utilizing the third dimension (vertical depth) by creating trenches that extend into the substrate. This allows capacitor electrodes and dielectric layers to be stacked vertically, achieving high capacitance values without occupying additional lateral area on the IC surface.
Solution Approach 2:
The patent implements a nested structure where capacitor electrodes and dielectric layers are alternately stacked within trenches formed in the substrate. Multiple capacitor elements are nested within the same trench volume, with inner electrodes surrounded by dielectric layers, creating a compact multi-layer capacitor configuration that maximizes capacitance density within the available space.
2Adaptability or versatility
If traditional discrete passive devices are mounted on PCBs, then functionality is achieved, but manufacturing cost increases
Solution Approach 1:
The patent merges the capacitor structure with the IC substrate itself, integrating passive capacitor elements directly into the semiconductor device. This consolidation eliminates the need for separate discrete capacitor components and their associated mounting processes, thereby reducing manufacturing complexity and cost while maintaining the required functionality.
Solution Approach 2:
The substrate serves multiple functions: it acts as both the mechanical support for the IC and as the medium containing the capacitor structures. The trenches in the substrate simultaneously provide mechanical support and house the capacitor electrodes and dielectric layers, reducing the total component count and simplifying the overall device architecture.
3Quantity of substance
If traditional discrete passive devices are mounted on PCBs, then capacitance function is achieved, but surface area on PCB increases
Solution Approach 1:
The patent transitions from two-dimensional planar capacitor layouts on the PCB surface to three-dimensional vertical stacking within substrate trenches. By utilizing the vertical dimension through trench depth and multi-layer electrode stacking, the solution achieves high capacitance values without requiring additional lateral surface area on the PCB or IC.
4Quantity of substance
If MIM or MOM capacitors are used for large capacitance values, then capacitance is improved, but device complexity increases
Solution Approach 1:
The patent combines the capacitor fabrication process with the existing IC manufacturing workflow. The trenches are formed using standard semiconductor processing techniques, and the electrode and dielectric layer deposition integrates with the existing multi-layer interconnect fabrication steps, thereby achieving large capacitance values without significantly increasing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the overall area impact on ICs, lowers manufacturing costs, and increases capacitance values in a compact form factor, enhancing mobile device performance and functionality.
Implementation Method 1
a capacitor dielectric layer in the trench and overlying the inner capacitor electrode
Implementation Method 2
a capacitor dielectric layer in the trench and overlying the inner capacitor electrode
Data Source
AI summary
Some embodiments relate to a method. In the method, semiconductor devices are formed on a frontside of a semiconductor substrate. A trench is formed in a backside of the semiconductor substrate. Conductive and insulating layers are alternatingly formed in the trench on the backside of the semiconductor substrate to establish a backside capacitor. A backside interconnect structure is formed on the backside of the semiconductor substrate to couple to capacitor electrodes of the backside capacitor.