Backside Trench Contact Structure With Plug-Last Power Delivery
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits faces challenges due to variability in conventional fabrication processes, leading to difficulties in extending these processes into the 10 nanometer node or sub-10 nanometer range, with issues such as etch loading effects in backside trench contact formation and high electrical resistance in power delivery networks.
Innovation Solution
A plug last approach is adopted for backside trench contact etch, where a backside trench contact grating is etched into the substrate, followed by patterning and filling plugs to their final height, and depositing backside trench contact placeholder material, which eliminates etch loading effects and ensures uniformity in poly profile/spacer between trench contact lines, and power is delivered from the wafer's backside to reduce interconnect stress and improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for backside trench contact formation, then existing process infrastructure can be maintained, but etch loading effects occur and manufacturing precision deteriorates at 10 nanometer node and below
Solution Approach 1:
The patent inverts the conventional fabrication sequence by performing the backside trench contact etch after device formation rather than before. This reversal eliminates etch loading effects that plague conventional approaches, as the etch is performed on a planarized surface with uniform depth requirements, thereby achieving superior manufacturing precision at 10 nanometer node and below while managing process complexity through the plug last approach
2Reliability
If power is delivered from the front side of the wafer, then existing interconnect architectures can be maintained, but power network resistance increases and device performance deteriorates
Solution Approach 1:
The patent transitions power delivery from the traditional front-side (two-dimensional planar) approach to a backside (three-dimensional vertical) approach. By delivering power through the backside of the wafer and using the plug last methodology to create low-resistance contact paths, the invention significantly reduces power network resistance and improves device performance while managing interconnect complexity through integrated process design
3Productivity
If multi-gate transistor dimensions are scaled down to increase device density, then chip capacity increases, but process variability increases and manufacturing becomes more difficult
Solution Approach 1:
The patent applies preliminary actions by performing surface planarization and preparing the backside surface before the final trench contact etch. This preliminary preparation ensures uniform etch conditions across the entire wafer surface, reducing process variability even as device dimensions are scaled down to increase density. The plug last approach further ensures that final contact dimensions are precisely controlled after all other variations are eliminated
Data Source
Figure 1
Figure 2A~2B
Figure 2C~2D
AI summary
Integrated circuit structures having backside plug last approach are described. In an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires or a fin. A gate stack is over the plurality of horizontally stacked nanowires or the fin. A conductive trench contact structure is at a level below the plurality of horizontally stacked nanowires or the fin, the conductive trench contact structure having outwardly tapered sidewalls from a top of the conductive trench contact structure to a bottom of the conductive trench contact structure.