Backside Trench Nanosheet Transistor Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Nanosheet transistors in integrated circuits face issues such as parasitic capacitance and potential short-circuiting due to a floating nanosheet, which affect performance and wafer yield.
Innovation Solution
A backside trench is etched through the substrate to remove the lowest nanosheet of a first transistor, replacing it with a dielectric material, while the second transistor maintains all nanosheets, thereby reducing parasitic capacitance and short-circuit risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all nanosheets are retained in the transistor structure, then the transistor maintains maximum channel capacity, but parasitic capacitance increases and short-circuit risks occur due to floating nanosheets
Solution Approach 1:
The patent removes the lowest nanosheet from the transistor structure through a backside trench etch process. This extraction eliminates the floating nanosheet that causes parasitic capacitance and potential short-circuiting, while preserving the functional nanosheets that contribute to channel capacity. The removed nanosheet is replaced with dielectric material to complete the isolation.
2Reliability
If the lowest nanosheet is removed to reduce parasitic capacitance, then reliability improves, but the transistor loses one channel region
Solution Approach 1:
The patent applies different treatments to different nanosheets within the same transistor structure. The lowest nanosheet is removed to eliminate harmful parasitic effects, while the upper nanosheets are retained to maintain channel capacity. This local differentiation optimizes overall transistor performance by eliminating defects while preserving functional elements.
3Object-generated harmful factors
If a backside trench is etched to remove the lowest nanosheet, then parasitic capacitance is reduced, but the manufacturing process complexity increases
Solution Approach 1:
Instead of addressing the floating nanosheet problem from the front side of the substrate, the patent introduces a backside trench that accesses the lowest nanosheet from the opposite dimension. This approach isolates the complex removal operation to a specific location through the substrate thickness, enabling precise elimination of the problematic nanosheet without affecting the overall transistor structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance and wafer yield by ensuring transistors with different numbers of active nanosheets without performance drawbacks, enhancing transconductance and reducing leakage currents.
Implementation Method 1
removing a lowest of the first semiconductor nanosheets by performing an etching process
Data Source
AI summary
An integrated circuit includes a first nanosheet transistor and a second nanosheet transistor on a substrate. The integrated circuit includes a backside trench through the substrate that removes a lowest semiconductor nanosheet of the first nanosheet transistor while leaving the lowest semiconductor nanosheet of the second nanosheet transistor. The backside trench is filled with a dielectric material.