Backside TSV Interconnect Structure for 3DIC Alignment and Yield
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and efficient interconnects in three-dimensional integrated circuits (3DICs), particularly in forming through-silicon vias (TSVs) that require precise alignment and fabrication on silicon-on-insulator substrates, leading to increased costs and reduced yield.
Innovation Solution
A method involving the formation of a stack structure with shallow trench isolation, contact etch stop layer, and interlayer dielectric layers, followed by multiple etching stages to create a TSV on the backside of a top wafer, using hybrid bonding and edge trimming to align and connect metal interconnections, allowing direct fabrication on bulk silicon substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If TSV fabrication is performed on silicon-on-insulator substrates using conventional methods, then alignment precision can be maintained, but manufacturing cost increases and yield decreases
Solution Approach 1:
The patent inverts the conventional TSV fabrication approach by performing TSV formation on bulk silicon substrates instead of silicon-on-insulator substrates. This inversion eliminates the need for complex intermediate processing steps required for SOI substrates, thereby reducing manufacturing costs while maintaining alignment precision through the bonding interface design
2Manufacturing precision
If TSV fabrication is performed on silicon-on-insulator substrates using conventional methods, then alignment precision can be maintained, but production yield decreases
Solution Approach 1:
The patent inverts the conventional TSV fabrication approach by performing TSV formation on bulk silicon substrates instead of silicon-on-insulator substrates. This inversion eliminates the need for complex intermediate processing steps required for SOI substrates, thereby reducing manufacturing costs while maintaining alignment precision through the bonding interface design
Solution Approach 2:
The patent extracts and eliminates the insulator layer from the substrate structure, working directly on bulk silicon substrates. This extraction simplifies the fabrication process by removing the need to navigate through multiple layers and interfaces, thereby improving production yield while maintaining alignment precision
3Ease of manufacture
If conventional TSV-via-middle methods are used, then fabrication process can be simplified, but integration density and performance are limited
Solution Approach 1:
The patent transitions from planar interconnect architecture to three-dimensional vertical interconnect architecture through TSV formation. This dimensional change enables stacking of multiple chip layers, thereby achieving high integration density while maintaining fabrication process simplicity through the bulk silicon substrate approach
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of first providing a stack structure having a shallow trench isolation (STI) under a first substrate, a contact etch stop layer (CESL) under the STI, an interlayer dielectric (ILD) layer under the CESL, and a first metal interconnection under the ILD layer and then forming a second metal interconnection penetrating through the first substrate, the STI, the CESL, and the ILD layer to contact the first metal interconnection and a liner adjacent to a sidewall of the second metal interconnection.