Back-Side TSV Interconnect Layout for Smaller Bond Pads

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Solution Overview

Problem

The existing integrated chip designs face limitations in routing capability due to the large size of redistribution vias (RV) and conductive bond pads, which restrict the flexibility and performance of metal interconnects.

Innovation Solution

The integration of a back-side through-substrate-via (BTSV) that directly connects metal interconnect layers to a conductive bond pad, reducing the size of the bond pad and enhancing routing capabilities by eliminating the need for a redistribution layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a conventional bond pad structure with thick metal layer is used, then external connectivity is provided, but routing flexibility and performance are restricted due to large size

Engineering Contradiction:
Improverouting flexibilityVSAvoidbond pad size
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent introduces a vertical via structure that extends through the substrate thickness, adding a dimensional pathway from the front surface to the back surface. This allows routing to occur in the vertical dimension rather than being constrained to horizontal plane routing, thereby improving routing flexibility without increasing the horizontal bond pad area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The connection path is segmented into multiple parts: front surface metal interconnect, vertical through-substrate via, and back surface metal interconnect. This segmentation allows each segment to be optimized independently, enabling smaller overall bond pad area while maintaining routing capability.

Inventive Principle:
Principle #1Segmentation

2Reliability

If redistribution vias with large size are used, then electrical connection is established, but routing capability is limited

Engineering Contradiction:
Improveelectrical connectionVSAvoidrouting capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The via structure transitions from horizontal redistribution in the metal interconnect layers to vertical routing through the substrate thickness. This dimensional change provides additional routing paths that are not constrained by the horizontal layout, thereby improving routing capability while maintaining reliable electrical connection.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The vertical via acts as an intermediary element that connects the front surface metal interconnect to the back surface metal interconnect. This intermediary structure enables routing flexibility by providing a dedicated vertical pathway that mediates between the front and back surface connections.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If thick metal interconnect layers are used, then conductive connection is provided, but path length is increased reducing performance

Engineering Contradiction:
Improveconductive connectionVSAvoidsignal path length
Core Design Contradiction:
ReliabilityVSLength of moving object

Solution Approach 1:

Instead of extending metal interconnect layers horizontally across the substrate surface, the patent inverts the approach by creating a vertical via that penetrates through the substrate thickness. This inversion of the routing direction from horizontal to vertical shortens the signal path length while maintaining conductive connection reliability.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The signal path is redirected from the horizontal plane to the vertical dimension through the through-substrate via. This dimensional change creates a more direct routing path that reduces the overall signal travel distance, thereby improving performance while maintaining reliable conduction.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12142569B2Integrated chip for standard logic performance improvement having a back-side through-substrate-via and method for forming the integrated chip
Publication Date: 2024.11.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12142569B2 patent drawing
  • US12142569B2 patent drawing
  • US12142569B2 patent drawing

AI summary

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first plurality of interconnects within a first inter-level dielectric (ILD) structure disposed along a first side of a first substrate. A conductive pad is arranged along a second side of the first substrate. A first through-substrate-via (TSV) physically contacts an interconnect of the first plurality of interconnects and a first surface of the conductive pad. A second plurality of interconnects are within a second ILD structure disposed on a second substrate. A second TSV extends from an interconnect of the second plurality of interconnects to through the second substrate. A conductive bump is arranged on a second surface of the conductive pad opposing the first surface. The second TSV has a greater width than the first TSV.