Backside TSV Connection Layout for Buried Power Rail Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of power delivery networks in semiconductor processing is challenging due to increased device density, leading to issues with wafer distortion and alignment of Through Semiconductor Via (TSV) connections, particularly in the 'via-last' approach, and connectivity problems with buried power rails due to small conductive areas.
Innovation Solution
A method involving etching via openings from the front of a semiconductor substrate, filling them with a sacrificial material, and then bonding the substrate to a carrier wafer, followed by thinning and removing the sacrificial material to create a conductive TSV connection, which includes forming a conductive pad integral with buried interconnect rails, enhancing alignment and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the via-last approach is used to integrate TSV connections, then the power delivery network can be segregated from signal carrying wiring, but wafer distortion during bonding causes non-linear deformation of buried rail patterns making perfect alignment impossible
Solution Approach 1:
The patent applies preliminary action by forming TSV openings and filling them with sacrificial material before bonding the wafer to the carrier. This sequence allows the wafer to be thinned and processed without the TSV structures being present during bonding, thereby avoiding the alignment issues caused by wafer distortion. The sacrificial material is later removed and replaced with conductive material after bonding is complete.
2Reliability
If metallized TSVs are integrated in high density, then connectivity is improved, but significant pattern distortions are induced due to stress
Solution Approach 1:
The patent forms TSV openings and fills them with sacrificial material before integrating the metallization layers, rather than filling them with metal before bonding. This preliminary formation of the TSV structures allows the subsequent metallization to be deposited without inducing stress-related pattern distortions, as the TSV openings provide a stress-relief structure during the metallization process.
3Productivity
If the conductive area contacted from the back of the substrate is made small, then device density is increased, but resistivity of the electrical path becomes unsatisfactory
Solution Approach 1:
The patent extends the conductive path from the back surface into the bulk substrate by forming deep TSV openings that penetrate through the substrate thickness. This dimensional extension allows the contact area to be distributed vertically through the substrate, providing sufficient conductive cross-section for low resistivity while maintaining small footprint on the back surface for high device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the alignment and connectivity of TSV connections, reducing residual overlay variations and increasing the contact area with buried power rails, thereby enhancing the power delivery network's efficiency and reliability.
Implementation Method 1
etching a via opening in the top layer, stopping on the etch stop layer
Implementation Method 2
bonding the front side of the substrate to a carrier wafer
Implementation Method 3
the substrate is thinned by removing the bulk wafer, using at the end an etch process that stops on the etch stop layer
Data Source
Figure 1a~1c
Figure 1d~1i
Figure 1j~1o
AI summary
The invention is related to methods for producing an interconnect structure (36) on the back side of an integrated circuit chip, the interconnect structure being connected to the front side of the IC by at least one through semiconductor via (TSV) connection (35). According to a first aspect of the invention, a via opening (7) is etched in a top semiconductor layer (3), stopping on an etch stop layer (2) of a substrate. The via opening is filled with a sacrificial material, thereby forming a sacrificial pillar (10). Then FEOL and BEOL portions are processed and the substrate is thinned, using at the end an etch process that stops on the etch stop layer (2). Said etch stop layer and the sacrificial pillar are removed also, creating a cavity (30) in which is exposed an electrically conductive structure of the FEOL portion, for example a buried interconnect rail (17). The TSV connection is produced by filling the cavity with an electrically conductive material, followed by producing the backside interconnect structure. According to second aspect, the sacrificial pillar (10) is reduced in height by partially etching back the pillar through the opening of a trench (42) that intersects the pillar, the trench being intended for the production of a buried interconnect rail (17). Filling of the trench with a conductive material also fills the cavity created by etching back the pillar. This results in a conductive pad that is integral with the buried interconnect rail formed in the trench. After thinning the substrate from the back, the reduced-height pillar (10') is removed and replaced by a conductive material, thereby creating the TSV connection (35).